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/Zephyr-latest/modules/hal_silabs/simplicity_sdk/config/
Dsl_clock_manager_oscillator_config.h17 #define SL_CLOCK_MANAGER_HFXO_FREQ DT_PROP(DT_NODELABEL(hfxo), clock_frequency)
33 (DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 1500000 ? 1000000U \
34 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 3000000 ? 2000000U \
35 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 5500000 ? 4000000U \
36 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 10000000 ? 7000000U \
37 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 14500000 ? 13000000U \
38 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 17500000 ? 16000000U \
39 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 23000000 ? 19000000U \
40 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 29000000 ? 26000000U \
41 : DT_PROP(DT_NODELABEL(hfrcodpll), clock_frequency) < 35000000 ? 32000000U \
[all …]
/Zephyr-latest/drivers/clock_control/
Dclock_control_pwm.c33 uint32_t clock_frequency; member
50 if (data->clock_frequency == 0) { in clock_control_pwm_on()
61 if (cycles_per_sec % data->clock_frequency > 0) { in clock_control_pwm_on()
65 period_cycles = cycles_per_sec / data->clock_frequency; in clock_control_pwm_on()
92 if (data->clock_frequency > 0) { in clock_control_pwm_get_rate()
93 *rate = data->clock_frequency; in clock_control_pwm_get_rate()
112 if (data->clock_frequency == rate_hz && data->is_enabled) { in clock_control_pwm_set_rate()
116 data->clock_frequency = rate_hz; in clock_control_pwm_set_rate()
152 .clock_frequency = DT_INST_PROP_OR(i, clock_frequency, 0), \
Dclock_control_rpi_pico.c78 (DT_PROP(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, pll), 0), clock_frequency) / \
81 #define CLOCK_FREQ_clk_gpout0 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout0), clock_frequency)
82 #define CLOCK_FREQ_clk_gpout1 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout1), clock_frequency)
83 #define CLOCK_FREQ_clk_gpout2 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout2), clock_frequency)
84 #define CLOCK_FREQ_clk_gpout3 DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_gpout3), clock_frequency)
85 #define CLOCK_FREQ_clk_hstx DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_hstx), clock_frequency)
86 #define CLOCK_FREQ_clk_ref DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_ref), clock_frequency)
87 #define CLOCK_FREQ_clk_sys DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_sys), clock_frequency)
88 #define CLOCK_FREQ_clk_usb DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_usb), clock_frequency)
89 #define CLOCK_FREQ_clk_adc DT_PROP(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk_adc), clock_frequency)
[all …]
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dadi_max32_clock_control.h42 #define ADI_MAX32_CLK_IPO_FREQ DT_PROP(DT_NODELABEL(clk_ipo), clock_frequency)
43 #define ADI_MAX32_CLK_ERFO_FREQ DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0)
44 #define ADI_MAX32_CLK_IBRO_FREQ DT_PROP(DT_NODELABEL(clk_ibro), clock_frequency)
45 #define ADI_MAX32_CLK_ISO_FREQ DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0)
46 #define ADI_MAX32_CLK_INRO_FREQ DT_PROP(DT_NODELABEL(clk_inro), clock_frequency)
47 #define ADI_MAX32_CLK_ERTCO_FREQ DT_PROP(DT_NODELABEL(clk_ertco), clock_frequency)
48 #define ADI_MAX32_CLK_IPLL_FREQ DT_PROP_OR(DT_NODELABEL(clk_ipll), clock_frequency, 0)
49 #define ADI_MAX32_CLK_EBO_FREQ DT_PROP_OR(DT_NODELABEL(clk_ebo), clock_frequency, 0)
51 #define ADI_MAX32_CLK_EXTCLK_FREQ DT_PROP_OR(DT_NODELABEL(clk_extclk), clock_frequency, 0)
Dstm32_clock_control.h317 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
322 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency)
365 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency)
372 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency)
375 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency)
378 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency)
386 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
393 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
402 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
406 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
[all …]
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc.c60 #if ((DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_16MHZ) && \
61 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_24MHZ) && \
62 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_32MHZ) && \
63 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_48MHZ) && \
64 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_64MHZ) && \
65 (DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency) != CLK_96MHZ))
76 unsigned int cclk = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency); in soc_early_init_hook()
/Zephyr-latest/drivers/stepper/adi_tmc/
Dadi_tmc5xxx_common.h37 uint32_t clock_frequency) in tmc5xxx_calculate_velocity_from_hz_to_fclk() argument
39 __ASSERT_NO_MSG(clock_frequency); in tmc5xxx_calculate_velocity_from_hz_to_fclk()
40 return (velocity_hz << TMC5XXX_CLOCK_FREQ_SHIFT) / clock_frequency; in tmc5xxx_calculate_velocity_from_hz_to_fclk()
/Zephyr-latest/samples/boards/st/i2c_timing/src/
Dmain.c39 (DT_PROP(I2C_DEV_NODE, clock_frequency) == 100000)) { in main()
42 (DT_PROP(I2C_DEV_NODE, clock_frequency) == 400000)) { in main()
45 (DT_PROP(I2C_DEV_NODE, clock_frequency) == 1000000)) { in main()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dsoc.c55 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
57 #elif MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
70 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
72 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
74 #elif MHZ(56) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
76 #elif MHZ(60) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wdog32.c25 #if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency)
26 uint32_t clock_frequency; member
94 #if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency) in mcux_wdog32_install_timeout()
95 clock_freq = config->clock_frequency; in mcux_wdog32_install_timeout()
195 #if DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, clocks), clock_frequency)
196 .clock_frequency = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
Dwdt_intel_adsp.c226 #if !(DT_NODE_HAS_PROP(DEV_NODE, clock_frequency) || DT_NODE_HAS_PROP(DEV_NODE, clocks))
232 COND_CODE_1(DT_NODE_HAS_PROP(DEV_NODE, clock_frequency),
233 (.clk_freq = DT_PROP(DEV_NODE, clock_frequency)),
234 (.clk_freq = DT_PROP_BY_PHANDLE(DEV_NODE, clocks, clock_frequency))
Dwdt_dw.c232 !(DT_INST_NODE_HAS_PROP(inst, clock_frequency) || DT_INST_NODE_HAS_PROP(inst, clocks)) ||
272 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, clock_frequency), \
273 (.clk_freq = DT_INST_PROP(inst, clock_frequency)), \
276 (.clk_freq = DT_INST_PROP_BY_PHANDLE(inst, clocks, clock_frequency))))), \
/Zephyr-latest/soc/intel/intel_adsp/common/
Dclk.c125 [ADSP_CLOCK_SOURCE_XTAL_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
133 [ADSP_CLOCK_SOURCE_AUDIO_CARDINAL] = { DT_PROP(DT_NODELABEL(audioclk), clock_frequency) },
136 [ADSP_CLOCK_SOURCE_AUDIO_PLL_FIXED] = { DT_PROP(DT_NODELABEL(pllclk), clock_frequency) },
140 [ADSP_CLOCK_SOURCE_WOV_RING_OSC] = { DT_PROP(DT_NODELABEL(sysclk), clock_frequency) },
/Zephyr-latest/drivers/pwm/
Dpwm_b91.c16 uint32_t clock_frequency; member
31 pwm_clk_div = sys_clk.pclk * 1000 * 1000 / config->clock_frequency - 1; in pwm_b91_init()
124 .clock_frequency = DT_INST_PROP(n, clock_frequency), \
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dsoc.c144 clock_frequency)); in clock_init()
146 clock_frequency)); in clock_init()
225 clock_frequency)) - 1); in clock_init()
249 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
251 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); in clock_init()
260 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); in clock_init()
262 DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); in clock_init()
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dsoc.c71 .freq = DT_PROP(SCG_CLOCK_NODE(sosc_clk), clock_frequency),
89 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
91 #elif MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
107 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
109 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
111 #elif MHZ(56) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
113 #elif MHZ(60) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c13 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
15 BUILD_ASSERT(KHZ(125125) == DT_PROP(DT_NODELABEL(pclk), clock_frequency),
Dsoc.h16 DT_PROP(DT_NODELABEL(pclk), clock_frequency)
/Zephyr-latest/soc/atmel/sam/common/
Datmel_sam_dt.h19 DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
/Zephyr-latest/soc/snps/arc_iot/
Dsoc.c16 #define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dsoc.h19 DT_PROP_BY_PHANDLE_IDX(DT_NODELABEL(tlclk), clocks, 0, clock_frequency)
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dsoc.h19 DT_PROP_BY_PHANDLE_IDX(DT_NODELABEL(tlclk), clocks, 0, clock_frequency)
Dclock.c12 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
/Zephyr-latest/drivers/spi/
Dspi_gecko_eusart.c38 uint32_t clock_frequency; member
94 if (gecko_config->clock_frequency > spi_frequency) { in spi_eusart_config()
98 spi_frequency = MIN(gecko_config->clock_frequency, spi_frequency); in spi_eusart_config()
310 .clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000) \
/Zephyr-latest/soc/nordic/nrf92/
Dsoc.c72 DT_PROP(HSFLL_NODE, clock_frequency) / in trim_hsfll()
73 DT_PROP(DT_CLOCKS_CTLR(HSFLL_NODE), clock_frequency)); in trim_hsfll()

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