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Searched refs:clk_divider (Results 1 – 12 of 12) sorted by relevance

/Zephyr-latest/drivers/watchdog/
Dwdt_mcux_wdog32.c32 wdog32_clock_prescaler_t clk_divider; member
108 div = config->clk_divider == kWDOG32_ClockPrescalerDivide1 ? 1U : 256U; in mcux_wdog32_install_timeout()
130 data->wdog_config.prescaler = config->clk_divider; in mcux_wdog32_install_timeout()
204 .clk_divider =
205 TO_WDOG32_CLK_DIV(DT_INST_PROP(0, clk_divider)),
Dwdt_mcux_wwdt.c27 uint8_t clk_divider; member
93 CLOCK_SetClkDiv(kCLOCK_DivWdtClk, config->clk_divider, true); in mcux_wwdt_install_timeout()
187 .clk_divider =
188 DT_INST_PROP(0, clk_divider),
/Zephyr-latest/drivers/spi/
Dspi_litex.c249 .clk_divider_exists = DT_INST_REG_HAS_NAME(n, clk_divider), \
250 .clk_divider_addr = DT_INST_REG_ADDR_BY_NAME_OR(n, clk_divider, 0), \
/Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/
Dsoc.c312 DT_PROP(DT_NODELABEL(i3c0), clk_divider)); in clock_init()
324 CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); in clock_init()
/Zephyr-latest/drivers/adc/
Dadc_mcux_12b1msps_sar.c283 ASSERT_RT_ADC_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
293 TO_RT_ADC_CLOCK_DIV(DT_INST_PROP(n, clk_divider)), \
Dadc_mcux_adc12.c287 ASSERT_ADC12_CLK_DIV_VALID(DT_INST_PROP(n, clk_divider), \
295 TO_ADC12_CLOCK_DIV(DT_INST_PROP(n, clk_divider)),\
Dadc_vf610.c250 .divide_ratio = DT_INST_PROP(n, clk_divider), \
/Zephyr-latest/soc/nxp/lpc/lpc55xxx/
Dsoc.c342 DT_PROP(DT_NODELABEL(adc0), clk_divider), true); in clock_init()
/Zephyr-latest/drivers/can/
Dcan_stm32h7_fdcan.c263 .clock_divider = DT_INST_PROP_OR(n, clk_divider, 0) \
Dcan_stm32_fdcan.c594 .clock_divider = DT_INST_PROP_OR(inst, clk_divider, 0) \
/Zephyr-latest/boards/nxp/frdm_mcxn947/
Dboard.c370 CLOCK_SetClkDiv(kCLOCK_DivI3c1FClk, DT_PROP(DT_NODELABEL(i3c1), clk_divider)); in frdm_mcxn947_init()
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/
Dsoc.c311 DT_PROP(DT_NODELABEL(i3c0), clk_divider)); in rt5xx_clock_init()