Searched refs:bitstream (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-latest/scripts/west_commands/runners/ |
| D | xsdb.py | 15 def __init__(self, cfg: RunnerConfig, config=None, bitstream=None, argument
25 self.bitstream = bitstream
47 bitstream=args.bitstream, fsbl=args.fsbl)
50 if self.bitstream and self.fsbl:
51 cmd = ['xsdb', self.xsdb_cfg_file, self.elf_file, self.bitstream, self.fsbl]
52 elif self.bitstream:
53 cmd = ['xsdb', self.xsdb_cfg_file, self.elf_file, self.bitstream]
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| /Zephyr-latest/samples/drivers/fpga/fpga_controller/ |
| D | README.rst | 4 Load a bitstream into an FPGA and perform basic operations on it.
8 This module is an FPGA driver that can easily load a bitstream, reset it, check its status, enable …
58 Address of the bitstream (red): 0xADDR
59 Address of the bitstream (green): 0xADDR
60 Size of the bitstream (red): 75960
61 Size of the bitstream (green): 75960
73 FPGA: loading bitstream
76 The LED should start blinking (color depending on the selected bitstream).
77 To upload the bitstream again you need to reset the FPGA:
84 You can also use your own bitstream.
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| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/ |
| D | index.rst | 13 The bitstream (FPGA configuration file) can be obtained using both
47 bitstream for the FPGA on a Digilent Arty A7-35 Board or SDI-MIPI Video Converter. This can be achi…
59 In order to generate the bitstream,
70 …Generating the bitstream for the Digilent Arty A7-35 Board requires F4PGA toolchain installation. …
73 In order to generate the bitstream for the SDI-MIPI Video Converter, install
100 #. Generate the bitstream for the Arty 35T:
106 #. Generate the bitstream for the Arty 100T:
112 #. Generate the bitstream for the SDI-MIPI Video Converter:
120 You can also generate the bitstream using the `official LiteX repository <https://github.com/enjoy-…
161 If you were generating bitstream with the official LiteX SoC builder you need to pass an additional…
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_eos_s3.c | 107 volatile uint32_t *bitstream = (volatile uint32_t *)image_ptr; in eos_s3_fpga_load() local
110 PIF->CFG_DATA = *bitstream; in eos_s3_fpga_load()
111 bitstream++; in eos_s3_fpga_load()
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| /Zephyr-latest/boards/digilent/arty_a7/doc/ |
| D | index.rst | 15 bitstream.
113 First, configure the FPGA with the selected reference design FPGA bitstream
118 Another option for configuring the FPGA with the reference design bitstream is
137 The pre-built FPGA bitstream only works for Arty boards equipped with an
138 Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream
181 revert to the application stored in the block RAM within the FPGA bitstream
184 The steps to persist the application within the FPGA bitstream are covered by
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| /Zephyr-latest/scripts/west_commands/tests/ |
| D | test_xsdb.py | 55 bitstream=tc["bitstream"],
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| /Zephyr-latest/samples/boards/quicklogic/qomu/ |
| D | README.rst | 6 This sample demonstrates how to load bitstream on EOS-S3 FPGA and use the
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| /Zephyr-latest/drivers/sensor/ams/ens210/ |
| D | ens210.c | 22 static uint32_t ens210_crc7(uint32_t bitstream) in ens210_crc7() argument
26 uint32_t val = (bitstream << ENS210_CRC7_WIDTH) | ENS210_CRC7_IVEC; in ens210_crc7()
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| /Zephyr-latest/boards/efinix/titanium_ti60_f225/doc/ |
| D | index.rst | 43 The Zephyr RTOS has been verified using the SoC bitstream generated by Efinity IDE v2022.2.322.
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| /Zephyr-latest/boards/others/neorv32/doc/ |
| D | index.rst | 101 First, configure the FPGA with the NEORV32 bitstream as described in the NEORV32
155 revert to the application stored in the block RAM within the FPGA bitstream
158 The steps to persist the application within the FPGA bitstream are covered by
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| /Zephyr-latest/boards/snps/emsdp/doc/ |
| D | index.rst | 74 storage device. This allows an FPGA configuration bitstream to be dragged and dropped into
75 the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device
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