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/Zephyr-latest/arch/xtensa/core/
Dwindow_vectors.S133 s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
136 s32e a1, a9, -12 /* save a1 to call[j+1]'s stack frame */
137 s32e a2, a9, -8 /* save a2 to call[j+1]'s stack frame */
138 s32e a3, a9, -4 /* save a3 to call[j+1]'s stack frame */
162 l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
163 l32e a1, a9, -12 /* restore a1 from call[i+1]'s stack frame */
164 l32e a2, a9, -8 /* restore a2 from call[i+1]'s stack frame */
167 l32e a3, a9, -4 /* restore a3 from call[i+1]'s stack frame */
202 s32e a9, a0, -28 /* save a9 to end of call[j]'s stack frame */
235 l32e a9, a11, -28 /* restore a9 from end of call[i]'s stack frame */
Dcrt1.S44 # define ARG4 a9 /* 4th outgoing call argument */
167 l32i a9, a6, 4 /* get end address, assumed multiple of 4 */
169 sub a10, a9, a8 /* a10 = length, assumed a multiple of 4 */
Dsyscall_helper.c26 register uintptr_t a9 __asm__("%a9") = arg6; in xtensa_syscall_helper_args_6()
31 "r" (a5), "r" (a8), "r" (a9) in xtensa_syscall_helper_args_6()
Dcoredump.c74 uint32_t a9; member
168 arch_blk.r.a9 = frame->blks[regs_blk_remaining].r1; in arch_coredump_info_dump()
Duserspace.S170 mov a11, a9
172 mov a9, a5
329 l32i a9, a1, 8
Dthread.c116 frame->a9 = (uintptr_t)arg3; /* a9 */ in init_stack()
Dxtensa_asm2_util.S70 s32i a9, a1, 4
117 l32i a9, a2, 4
/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S404 movi a9, 0 /* cacheadrdis value */
406 wsr.cacheadrdis a9
413 slli a9, a9, 1 /* add a bit to cacheadrdis... */
414 addi a10, a9, 1 /* set that new bit if... */
415 moveqz a9, a10, a5 /* ... that region is non-cacheable */
430 movi a9, XCHAL_MPU_BG_CACHEADRDIS
432 wsr.cacheadrdis a9 /* update cacheadrdis */
/Zephyr-latest/boards/digilent/zybo/
Dzybo.dts40 compatible = "arm,cortex-a9";
46 compatible = "arm,cortex-a9";
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_context.h190 uintptr_t a9; member
211 uintptr_t a9; member
/Zephyr-latest/boards/qemu/cortex_a9/
Dboard.cmake9 set(QEMU_CPU_TYPE_${ARCH} cortex-a9)
Dqemu_cortex_a9.dts22 compatible = "arm,cortex-a9";
/Zephyr-latest/include/zephyr/arch/xtensa/
Dsyscall.h76 register uintptr_t a9 __asm__("%a9") = arg6; in arch_syscall_invoke6()
81 "r" (a5), "r" (a8), "r" (a9) in arch_syscall_invoke6()
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower_down.S36 #define temp_reg3 a9
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower_down_cavs.S42 #define temp_reg3 a9
/Zephyr-latest/dts/arm/intel_socfpga_std/
Dsocfpga.dtsi28 compatible = "arm,cortex-a9";
34 compatible = "arm,cortex-a9";
/Zephyr-latest/cmake/
Dgcc-m-cpu.cmake88 set(GCC_M_CPU cortex-a9)
/Zephyr-latest/dts/arm/nxp/
Dnxp_imx6sx_m4.dtsi20 compatible = "arm,cortex-a9";
/Zephyr-latest/boards/udoo/udoo_neo_full/doc/
Dindex.rst350 …processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:…