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/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h109 rur.fcr a0
110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
111 rur.fsr a0
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
132 l32i.n a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
133 wur.fcr a0
134 l32i.n a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
135 wur.fsr a0
167 rsr.sar a0
168 s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
[all …]
/Zephyr-latest/arch/xtensa/core/
Dxtensa_asm2_util.S154 l32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
155 wsr a0, ZSR_EPC
156 l32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
157 wsr a0, ZSR_EPS
168 l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
169 wsr a0, SAR
171 l32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
172 wsr a0, LBEG
173 l32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
174 wsr a0, LEND
[all …]
Duserspace.S29 movi a0, xtensa_is_user_context_epc
31 bne a0, a2, _not_checking_user_context
36 movi a0, PS_RING_MASK
38 and a2, a2, a0
49 rsr a0, ZSR_A0SAVE
56 rsr a0, ZSR_CPU
57 l32i a0, a0, ___cpu_t_current_OFFSET
58 l32i a0, a0, _thread_offset_to_psp
60 addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
62 s32i a1, a0, ___xtensa_irq_bsa_t_scratch_OFFSET
[all …]
Dwindow_vectors.S56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
100 rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
133 s32e a0, a9, -16 /* save a0 to call[j+1]'s stack frame */
134 l32e a0, a1, -12 /* a0 <- call[j-1]'s sp
139 s32e a4, a0, -32 /* save a4 to call[j]'s stack frame */
140 s32e a5, a0, -28 /* save a5 to call[j]'s stack frame */
141 s32e a6, a0, -24 /* save a6 to call[j]'s stack frame */
142 s32e a7, a0, -20 /* save a7 to call[j]'s stack frame */
162 l32e a0, a9, -16 /* restore a0 from call[i+1]'s stack frame */
[all …]
Dcrt1.S74 movi a0, 0 /* keep this register zero. */
147 movi a0, 0
171 s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
174 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
175 s32i a0, a8, 4
179 s32i a0, a8, 0 /* clear 16 bytes at a time... */
180 s32i a0, a8, 4
181 s32i a0, a8, 8
182 s32i a0, a8, 12
/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h44 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke6()
53 : "+r" (a0) in arch_syscall_invoke6()
57 return a0; in arch_syscall_invoke6()
65 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke5()
73 : "+r" (a0) in arch_syscall_invoke5()
76 return a0; in arch_syscall_invoke5()
83 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke4()
90 : "+r" (a0) in arch_syscall_invoke4()
93 return a0; in arch_syscall_invoke4()
100 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke3()
[all …]
/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S35 sll t1, t1, a0
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
70 lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
71 lw t1, __soc_esf_t_lpend0_OFFSET(a0)
72 lw t2, __soc_esf_t_lpcount0_OFFSET(a0)
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S42 csrrci a0, 0x345, MSTATUS_IEN
43 beqz a0, irq_done /* Check if original interrupt vanished. */
54 sub a0, a0, t0
56 slli a0, a0, (1)
57 add t0, t0, a0
60 lw a0, 0(t0)
73 csrrci a0, 0x345, MSTATUS_IEN
74 bnez a0, irq_loop
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c32 typedef void (*smc_cb_t)(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3,
40 uint32_t a0; member
54 void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_smc() argument
58 if (a0 == OPTEE_SMC_CALLS_UID) { in arm_smccc_smc()
59 res->a0 = OPTEE_MSG_UID_0; in arm_smccc_smc()
66 if (a0 == OPTEE_SMC_EXCHANGE_CAPABILITIES) { in arm_smccc_smc()
70 if (a0 == OPTEE_SMC_GET_THREAD_COUNT) { in arm_smccc_smc()
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
[all …]
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dentry.S17 la a0, __nuclei_start
20 bleu a1, a0, _start0800
22 bleu a1, a0, _start0800
23 la a0, _start0800
24 add a0, a0, a1
25 jr a0
/Zephyr-latest/arch/riscv/core/
Dswitch.S50 lr sp, _thread_offset_to_sp(a0)
54 lr tp, _thread_offset_to_tls(a0)
59 mv s0, a0
61 mv a0, s0
66 mv s0, a0
68 mv a0, s0
75 lb t0, _thread_offset_to_user_options(a0)
78 mv s0, a0
80 mv a0, s0
85 mv s0, a0
[all …]
Dpmp.S40 slli t1, a0, 4 /* 16-byte instruction blocks */
66 srli a0, a0, RV_REGSHIFT
67 slli t1, a0, 4 /* 16-byte instruction blocks */
80 addi a0, a0, 1
82 beq a0, a1, pmpcfg_done
92 slli a0, a0, 2 /* 4-byte instruction blocks */
93 add t0, t0, a0
Disr.S34 RV_E( op a0, __struct_arch_esf_a0_OFFSET(sp) );\
299 mv a0, sp
314 addi a0, sp, __struct_arch_esf_soc_context_OFFSET
330 bnez a0, is_interrupt
370 lr a0, ___cpu_t_current_OFFSET(s0)
384 mv a0, sp
424 lr a0, __struct_arch_esf_a0_OFFSET(sp)
433 lb t1, _thread_offset_to_exception_depth(a0)
435 sb t1, _thread_offset_to_exception_depth(a0)
447 li a0, 3
[all …]
Dsemihost.c23 register unsigned long a0 __asm__ ("a0") = instr; in semihost_exec()
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory"); in semihost_exec()
/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S92 movi a0, __memctl_default
93 wsr a0, MEMCTL
124 movi a0, ~MEMCTL_INV_EN
126 and a0, a4, a0
127 wsr a0, MEMCTL
138 movi a0, __memctl_default
139 wsr a0, MEMCTL
146 movi a0, 0
153 wsr a0, INTENABLE
161 wsr a0, CCOUNT
[all …]
/Zephyr-latest/soc/andestech/ae350/
Dsoc_irq.S28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
41 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc_irq.S32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/soc/wch/ch32v00x/
Dsoc_irq.S14 csrr a0, mcause
15 srli a0, a0, 31
Dvector.S23 li a0, 3
24 csrw mtvec, a0
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h15 unsigned long a0; member
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1,
53 void arm_smccc_smc(unsigned long a0, unsigned long a1,
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc_irq.S15 csrr a0, mcause
16 srli a0, a0, 31
/Zephyr-latest/samples/shields/lmp90100_evb/rtd/src/
Dmain.c28 const double a0 = 3.90802E-3; in rtd_temperature() local
32 temp = -nom * a0; in rtd_temperature()
33 temp += sqrt((nom * nom) * (a0 * a0) - 4.0 * nom * b0 * in rtd_temperature()
/Zephyr-latest/tests/arch/arm64/arm64_smc_call/src/
Dmain.c34 zassert_true(res.a0 > 0, "Wrong smc call count"); in ZTEST()
37 zassert_true((res.a0 >= 0 && res.a1 >= 0), in ZTEST()
41 zassert_true(res.a0 == SMC_UNK, "Wrong return code from smc call"); in ZTEST()
/Zephyr-latest/arch/mips/core/
Disr.S53 op a0, ESF_O(a0)(sp) ;\
116 li a0, CAUSE_IP_MASK
117 and a0, a0, t1
118 srl a0, a0, CAUSE_IP_SHIFT
124 bnez a0, is_interrupt
127 move a0, sp
155 move a0, zero
/Zephyr-latest/soc/nordic/common/vpr/
Dsoc_context.S14 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
19 lw t0, __soc_esf_t_minttresh_OFFSET(a0)

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