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Searched refs:XTENSA_WSR (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/soc/intel/intel_adsp/common/include/
Dcpu_init.h57 XTENSA_WSR("MEMCTL", reg); in cpu_early_init()
73 XTENSA_WSR("PREFCTL", reg); in cpu_early_init()
95 XTENSA_WSR("ATOMCTL", reg); in cpu_early_init()
99 XTENSA_WSR("INTENABLE", reg); in cpu_early_init()
108 XTENSA_WSR("VECBASE", reg); in cpu_early_init()
/Zephyr-latest/arch/xtensa/core/
Dprep_c.c43 XTENSA_WSR(ZSR_FLUSH_STR, 0); in z_prep_c()
55 XTENSA_WSR(ZSR_CPU_STR, cpu0); in z_prep_c()
Dvector_handlers.c495 XTENSA_WSR(ZSR_DEPC_SAVE_STR, 0); in xtensa_excint1_c()
Dptables.c323 XTENSA_WSR(ZSR_DEPC_SAVE_STR, 0); in xtensa_mmu_init()
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dpower.c165 XTENSA_WSR("PS", core_desc[core_id].ps); in _restore_core_context()
166 XTENSA_WSR("VECBASE", core_desc[core_id].vecbase); in _restore_core_context()
167 XTENSA_WSR("EXCSAVE2", core_desc[core_id].excsave2); in _restore_core_context()
168 XTENSA_WSR("EXCSAVE3", core_desc[core_id].excsave3); in _restore_core_context()
171 XTENSA_WSR("MISC0", core_desc[core_id].misc[0]); in _restore_core_context()
172 XTENSA_WSR("MISC1", core_desc[core_id].misc[1]); in _restore_core_context()
/Zephyr-latest/include/zephyr/arch/xtensa/
Darch_inlines.h34 #define XTENSA_WSR(sr, v) \ macro
/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dpower.c98 XTENSA_WSR("PS", core_desc[core_id].ps); in _restore_core_context()
99 XTENSA_WSR(ZSR_CPU_STR, core_desc[core_id].excsave2); in _restore_core_context()
/Zephyr-latest/doc/releases/
Drelease-notes-3.2.rst291 and :c:macro:`XTENSA_WSR` to give them proper namespace.