Searched refs:XTENSA_MMU_PERM_W (Results 1 – 3 of 3) sorted by relevance
/Zephyr-latest/soc/intel/intel_adsp/ace/ |
D | mmu_ace30.c | 27 .attrs = XTENSA_MMU_PERM_W, 34 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 46 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 52 .attrs = XTENSA_MMU_PERM_W, 58 .attrs = XTENSA_MMU_PERM_W, 64 .attrs = XTENSA_MMU_PERM_W, 70 .attrs = XTENSA_MMU_PERM_W, 77 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 99 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 106 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, [all …]
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/Zephyr-latest/include/zephyr/arch/xtensa/ |
D | xtensa_mmu.h | 27 #define XTENSA_MMU_PERM_W BIT(1) macro 30 #define XTENSA_MMU_PERM_WX (XTENSA_MMU_PERM_W | XTENSA_MMU_PERM_X) 50 #define K_MEM_PARTITION_IS_WRITABLE(attr) (((attr) & XTENSA_MMU_PERM_W) != 0) 55 ((k_mem_partition_attr_t) {XTENSA_MMU_PERM_W | XTENSA_MMU_MAP_USER})
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/Zephyr-latest/arch/xtensa/core/ |
D | ptables.c | 125 .attrs = XTENSA_MMU_PERM_W, 127 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 137 .attrs = XTENSA_MMU_PERM_W, 139 .attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 299 XTENSA_MMU_PAGE_TABLE_ATTR | XTENSA_MMU_PERM_W); in xtensa_init_page_tables() 302 XTENSA_MMU_PAGE_TABLE_ATTR | XTENSA_MMU_PERM_W); in xtensa_init_page_tables() 503 xtensa_flags |= XTENSA_MMU_PERM_W; in arch_mem_map() 922 XTENSA_MMU_KERNEL_RING, XTENSA_MMU_PERM_W, option); in reset_region() 933 XTENSA_MMU_USER_RING, XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, 0); in xtensa_user_stack_perms() 984 XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB, in arch_mem_domain_thread_add() [all …]
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