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Searched refs:TIMIN_SCLK_DIV_MSK (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.h97 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0) macro
Dspi_andes_atcspi200.c66 sys_clear_bits(SPI_TIMIN(cfg->base), TIMIN_SCLK_DIV_MSK); in spi_config()
/Zephyr-latest/drivers/flash/
Dflash_andes_qspi.h102 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0) macro
Dflash_andes_qspi.c703 sys_set_bits(QSPI_TIMIN(base), TIMIN_SCLK_DIV_MSK); in qspi_andes_configure()