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Searched refs:STM32_SRC_SYSCLK (Results 1 – 25 of 33) sorted by relevance

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/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/
Dtest_stm32_clock_configuration_sdmmc.c51 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
70 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
103 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
Dtest_stm32_clock_configuration_adc.c97 case STM32_SRC_SYSCLK: in ZTEST()
Dtest_stm32_clock_configuration_i2c.c47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dspi1_sysclk.overlay15 <&rcc STM32_SRC_SYSCLK SPI1_SEL(1)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32_common_clocks.h10 #define STM32_SRC_SYSCLK 0x001 macro
Dstm32wba_clock.h33 #define STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK
/Zephyr-latest/dts/arm/st/f4/
Dstm32f469.dtsi15 <&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Df4_sdmmc48_pll.overlay27 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
Dg0_i2c1_sysclk_lptim1_lsi.overlay69 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
Dwb_i2c1_sysclk_lptim1_lsi.overlay75 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
Dl4_i2c1_hsi_lptim1_lse.overlay77 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
Dl4_i2c1_sysclk_lptim1_lsi.overlay76 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>,
Dwl_i2c1_sysclk_lptim1_lsi.overlay72 <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>;
/Zephyr-latest/dts/arm/st/f3/
Dstm32f302.dtsi29 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
45 <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>;
Dstm32f303.dtsi29 <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/
Dtest_stm32_clock_configuration.c67 } else if (pclken[1].bus == STM32_SRC_SYSCLK) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wb0.c184 case STM32_SRC_SYSCLK: in enabled_clock()
472 case STM32_SRC_SYSCLK: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_wba.c46 if ((src_clk == STM32_SRC_SYSCLK) || in enabled_clock()
224 case STM32_SRC_SYSCLK: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h5.c121 if ((src_clk == STM32_SRC_SYSCLK) || in enabled_clock()
249 case STM32_SRC_SYSCLK: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_common.c125 case STM32_SRC_SYSCLK: in enabled_clock()
393 case STM32_SRC_SYSCLK: in stm32_clock_control_get_subsys_rate()
/Zephyr-latest/boards/st/nucleo_wb05kz/
Dnucleo_wb05kz.dts131 <&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>;
/Zephyr-latest/boards/st/nucleo_wb07cc/
Dnucleo_wb07cc.dts130 <&rcc STM32_SRC_SYSCLK SPI2_I2S2_SEL(1)>;
/Zephyr-latest/boards/st/nucleo_wb09ke/
Dnucleo_wb09ke.dts131 <&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>;
/Zephyr-latest/boards/st/nucleo_g071rb/
Dnucleo_g071rb.dts147 <&rcc STM32_SRC_SYSCLK ADC_SEL(0)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l4p5.dtsi372 <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,
386 <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>,

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