Home
last modified time | relevance | path

Searched refs:STM32_SRC_PLL3_Q (Results 1 – 7 of 7) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h35 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) macro
36 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
Dstm32h7_clock.h32 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) macro
33 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
Dstm32u5_clock.h37 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) macro
38 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
Dstm32h5_clock.h36 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) macro
37 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1)
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c139 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || in enabled_clock()
328 case STM32_SRC_PLL3_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c145 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || in enabled_clock()
343 case STM32_SRC_PLL3_Q: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c376 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
623 case STM32_SRC_PLL3_Q: