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Searched refs:STM32_SRC_PLL3_P (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pll3p_1_d1ppre_4.overlay28 <&rcc STM32_SRC_PLL3_P SPI123_SEL(2)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h34 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_T + 1) macro
35 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
Dstm32h7_clock.h31 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) macro
32 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
Dstm32u5_clock.h36 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) macro
37 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
Dstm32h5_clock.h35 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_R + 1) macro
36 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1)
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c73 } else if (pclken[1].bus == STM32_SRC_PLL3_P) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c138 ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) || in enabled_clock()
322 case STM32_SRC_PLL3_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c144 ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) || in enabled_clock()
337 case STM32_SRC_PLL3_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c375 ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
617 case STM32_SRC_PLL3_P: