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Searched refs:STM32_SRC_PLL2_P (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/
Dspi1_pll2p_1.overlay23 <&rcc STM32_SRC_PLL2_P SPI123_SEL(1)>;
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h29 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_S + 1) macro
30 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
Dstm32h7_clock.h28 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) macro
29 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
Dstm32u5_clock.h33 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) macro
34 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
Dstm32h5_clock.h32 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1) macro
33 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1)
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/
Dtest_stm32_clock_configuration.c69 } else if (pclken[1].bus == STM32_SRC_PLL2_P) { in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c135 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
302 case STM32_SRC_PLL2_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c141 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) || in enabled_clock()
317 case STM32_SRC_PLL2_P: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c372 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
583 case STM32_SRC_PLL2_P: