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Searched refs:STM32_SRC_PLL1_R (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32h7rs_clock.h27 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) macro
28 #define STM32_SRC_PLL1_S (STM32_SRC_PLL1_R + 1)
Dstm32h7_clock.h27 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) macro
28 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
Dstm32u5_clock.h32 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) macro
33 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
Dstm32h5_clock.h31 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) macro
32 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_R + 1)
Dstm32wba_clock.h30 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) macro
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_wba.c58 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) { in enabled_clock()
240 case STM32_SRC_PLL1_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h5.c134 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) || in enabled_clock()
295 case STM32_SRC_PLL1_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_u5.c140 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) || in enabled_clock()
311 case STM32_SRC_PLL1_R: in stm32_clock_control_get_subsys_rate()
Dclock_stm32_ll_h7.c372 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||
569 case STM32_SRC_PLL1_R: