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Searched refs:STM32_PLL_P_ENABLED (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_common.c198 if (!IS_ENABLED(STM32_PLL_P_ENABLED)) { in enabled_clock()
411 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in stm32_clock_control_get_subsys_rate()
602 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED in set_up_plls()
Dclock_stm32_ll_wba.c56 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
414 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h5.c132 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
482 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c138 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) || in enabled_clock()
570 if (IS_ENABLED(STM32_PLL_P_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c369 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
851 if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h163 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) macro