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Searched refs:STM32_PLL3_SRC_HSI (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c54 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
570 } else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) { in set_up_plls()
641 IS_ENABLED(STM32_PLL2_SRC_HSI) || IS_ENABLED(STM32_PLL3_SRC_HSI)) { in set_up_fixed_clock_sources()
Dclock_stm32_ll_u5.c59 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
655 } else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) { in set_up_plls()
Dclock_stm32_ll_n6.c58 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID) || in get_pllsrc_frequency()
716 } else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) { in set_up_plls()
Dclock_stm32_ll_h7.c690 + IS_ENABLED(STM32_PLL3_SRC_HSI)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h348 #define STM32_PLL3_SRC_HSI 1 macro