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Searched refs:STM32_PLL3_SRC_HSE (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c58 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
566 if (IS_ENABLED(STM32_PLL3_SRC_HSE)) { in set_up_plls()
Dclock_stm32_ll_u5.c63 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
651 if (IS_ENABLED(STM32_PLL3_SRC_HSE)) { in set_up_plls()
Dclock_stm32_ll_n6.c63 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID) || in get_pllsrc_frequency()
710 if (IS_ENABLED(STM32_PLL3_SRC_HSE)) { in set_up_plls()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h351 #define STM32_PLL3_SRC_HSE 1 macro