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Searched refs:STM32_PLL3_R_ENABLED (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c140 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { in enabled_clock()
604 if (IS_ENABLED(STM32_PLL3_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c146 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) { in enabled_clock()
688 if (IS_ENABLED(STM32_PLL3_R_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c378 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
966 if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h229 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r) macro