Home
last modified time | relevance | path

Searched refs:STM32_PLL3_Q_ENABLED (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c139 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || in enabled_clock()
599 if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_u5.c145 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) || in enabled_clock()
683 if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) { in set_up_plls()
Dclock_stm32_ll_h7.c377 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
961 if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h227 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q) macro