Searched refs:STM32_PLL3_M_DIVISOR (Results 1 – 4 of 4) sorted by relevance
/Zephyr-latest/drivers/clock_control/ |
D | clock_stm32_ll_h5.c | 324 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 330 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 336 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 571 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls() 578 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR); in set_up_plls()
|
D | clock_stm32_ll_u5.c | 339 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 345 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 351 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate() 659 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls() 664 LL_RCC_PLL3_SetDivider(STM32_PLL3_M_DIVISOR); in set_up_plls()
|
D | clock_stm32_ll_h7.c | 619 STM32_PLL3_M_DIVISOR, 625 STM32_PLL3_M_DIVISOR, 631 STM32_PLL3_M_DIVISOR, 638 STM32_PLL3_M_DIVISOR, 933 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range); 940 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
|
/Zephyr-latest/include/zephyr/drivers/clock_control/ |
D | stm32_clock_control.h | 217 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) macro
|