Searched refs:STM32_PLL3_M_DIVISOR (Results 1 – 5 of 5) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_h5.c | 325 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
331 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
337 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
576 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls()
583 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR); in set_up_plls()
|
| D | clock_stm32_ll_u5.c | 341 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
347 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
353 STM32_PLL3_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
661 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls()
666 LL_RCC_PLL3_SetDivider(STM32_PLL3_M_DIVISOR); in set_up_plls()
|
| D | clock_stm32_ll_h7.c | 622 STM32_PLL3_M_DIVISOR,
628 STM32_PLL3_M_DIVISOR,
634 STM32_PLL3_M_DIVISOR,
641 STM32_PLL3_M_DIVISOR,
936 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range);
943 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
|
| D | clock_stm32_ll_n6.c | 99 pllm_div = STM32_PLL3_M_DIVISOR; in get_pllout_frequency()
732 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR); in set_up_plls()
|
| /Zephyr-latest/include/zephyr/drivers/clock_control/ |
| D | stm32_clock_control.h | 223 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) macro
279 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) macro
|
