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Searched refs:STM32_PLL3_ENABLED (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c322 #if defined(STM32_PLL3_ENABLED) in stm32_clock_control_get_subsys_rate()
432 defined(STM32_PLL3_ENABLED) in set_up_plls()
564 #if defined(STM32_PLL3_ENABLED) in set_up_plls()
Dclock_stm32_ll_u5.c338 #if defined(STM32_PLL3_ENABLED) in stm32_clock_control_get_subsys_rate()
515 defined(STM32_PLL3_ENABLED) in set_up_plls()
649 #if defined(STM32_PLL3_ENABLED) in set_up_plls()
Dclock_stm32_ll_n6.c97 #if defined(STM32_PLL3_ENABLED) in get_pllout_frequency()
165 ((src_clk == STM32_SRC_PLL3) && IS_ENABLED(STM32_PLL3_ENABLED)) || in enabled_clock()
706 #if defined(STM32_PLL3_ENABLED) in set_up_plls()
Dclock_stm32_ll_h7.c619 #if defined(STM32_PLL3_ENABLED)
769 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || defined(STM32_PLL3_ENABLED)
935 #if defined(STM32_PLL3_ENABLED)
Dclock_stm32_ll_common.c238 if (!IS_ENABLED(STM32_PLL3_ENABLED)) { in enabled_clock()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h222 #define STM32_PLL3_ENABLED 1 macro
278 #define STM32_PLL3_ENABLED 1 macro