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Searched refs:STM32_PLL2_M_DIVISOR (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c304 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
310 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
316 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
517 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
524 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c585 STM32_PLL2_M_DIVISOR,
591 STM32_PLL2_M_DIVISOR,
597 STM32_PLL2_M_DIVISOR,
604 STM32_PLL2_M_DIVISOR,
610 STM32_PLL2_M_DIVISOR,
879 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range);
886 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
Dclock_stm32_ll_u5.c319 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
325 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
331 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
607 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
612 LL_RCC_PLL2_SetDivider(STM32_PLL2_M_DIVISOR); in set_up_plls()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h197 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) macro