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Searched refs:STM32_PLL2_M_DIVISOR (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c305 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
311 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
317 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
522 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
529 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_h7.c588 STM32_PLL2_M_DIVISOR,
594 STM32_PLL2_M_DIVISOR,
600 STM32_PLL2_M_DIVISOR,
607 STM32_PLL2_M_DIVISOR,
613 STM32_PLL2_M_DIVISOR,
882 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range);
889 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
Dclock_stm32_ll_u5.c321 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
327 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
333 STM32_PLL2_M_DIVISOR, in stm32_clock_control_get_subsys_rate()
609 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
614 LL_RCC_PLL2_SetDivider(STM32_PLL2_M_DIVISOR); in set_up_plls()
Dclock_stm32_ll_n6.c91 pllm_div = STM32_PLL2_M_DIVISOR; in get_pllout_frequency()
685 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR); in set_up_plls()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h203 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) macro
271 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) macro