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Searched refs:STM32_LSE_ENABLED (Results 1 – 8 of 8) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32f1.c170 if (IS_ENABLED(STM32_LSE_ENABLED)) { in config_enable_default_clocks()
Dclock_stm32_ll_u5.c134 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
281 #if defined(STM32_LSE_ENABLED) in stm32_clock_control_get_subsys_rate()
731 if (IS_ENABLED(STM32_LSE_ENABLED)) { in set_up_fixed_clock_sources()
773 __ASSERT(STM32_LSE_ENABLED, in set_up_fixed_clock_sources()
795 __ASSERT(STM32_LSE_ENABLED, in set_up_fixed_clock_sources()
Dclock_stm32_ll_wba.c54 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
245 #if defined(STM32_LSE_ENABLED) in stm32_clock_control_get_subsys_rate()
485 if (IS_ENABLED(STM32_LSE_ENABLED)) { in set_up_fixed_clock_sources()
Dclock_stm32_ll_h5.c129 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) || in enabled_clock()
266 #if defined(STM32_LSE_ENABLED) in stm32_clock_control_get_subsys_rate()
652 if (IS_ENABLED(STM32_LSE_ENABLED)) { in set_up_fixed_clock_sources()
Dclock_stm32_ll_wb0.c187 if (!IS_ENABLED(STM32_LSE_ENABLED)) { in enabled_clock()
571 if (IS_ENABLED(STM32_LSE_ENABLED)) { in set_up_fixed_clock_sources()
Dclock_stm32_ll_h7.c367 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
533 #if defined(STM32_LSE_ENABLED)
717 if (IS_ENABLED(STM32_LSE_ENABLED)) {
Dclock_stm32_ll_common.c156 if (!IS_ENABLED(STM32_LSE_ENABLED)) { in enabled_clock()
719 if (IS_ENABLED(STM32_LSE_ENABLED)) { in set_up_fixed_clock_sources()
/Zephyr-latest/include/zephyr/drivers/clock_control/
Dstm32_clock_control.h316 #define STM32_LSE_ENABLED 1 macro
321 #define STM32_LSE_ENABLED 1 macro
326 #define STM32_LSE_ENABLED 0 macro