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Searched refs:SPI_CTRL (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.c101 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_THRES_MSK); in spi_config()
102 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_RX_THRES_MSK); in spi_config()
104 sys_set_bits(SPI_CTRL(cfg->base), TX_FIFO_THRESHOLD << CTRL_TX_THRES_OFFSET); in spi_config()
105 sys_set_bits(SPI_CTRL(cfg->base), RX_FIFO_THRESHOLD << CTRL_RX_THRES_OFFSET); in spi_config()
203 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_enable()
210 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_TX_DMA_EN_MSK); in spi_tx_dma_disable()
217 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_enable()
224 sys_clear_bits(SPI_CTRL(cfg->base), CTRL_RX_DMA_EN_MSK); in spi_rx_dma_disable()
622 sys_set_bits(SPI_CTRL(cfg->base), CTRL_TX_FIFO_RST_MSK); in transceive()
623 sys_set_bits(SPI_CTRL(cfg->base), CTRL_RX_FIFO_RST_MSK); in transceive()
Dspi_andes_atcspi200.h34 #define SPI_CTRL(base) (base + REG_CTRL) macro
/Zephyr-latest/include/zephyr/arch/riscv/common/
Dlinker.ld61 #define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash)) macro
64 (DT_REG_ADDR_BY_NAME_OR(SPI_CTRL, FLASH_MMAP_NAME, DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)) + \
68 (DT_REG_SIZE_BY_NAME_OR(SPI_CTRL, FLASH_MMAP_NAME, DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)) - \
/Zephyr-latest/soc/andestech/ae350/
Dlinker.ld47 #define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash)) macro
48 #define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
49 #define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dlinker.ld40 #define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash)) macro
41 #define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
42 #define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
/Zephyr-latest/drivers/mipi_dbi/
Dmipi_dbi_nxp_lcdic.c304 reg = base->SPI_CTRL; in mipi_dbi_lcdic_configure()
312 base->SPI_CTRL = reg; in mipi_dbi_lcdic_configure()