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Searched refs:SCR (Results 1 – 17 of 17) sorted by relevance

/Zephyr-latest/soc/microchip/mec/mec172x/
Dpower.c72 SCB->SCR |= BIT(2); in z_power_soc_deep_sleep()
89 SCB->SCR &= ~BIT(2); in z_power_soc_deep_sleep()
129 SCB->SCR &= ~BIT(2); in z_power_soc_sleep()
/Zephyr-latest/soc/nxp/kinetis/ke1xf/
Dpower.c37 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
60 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
/Zephyr-latest/soc/nxp/kinetis/ke1xz/
Dpower.c35 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in pm_state_set()
57 SCB->SCR &= ~(SCB_SCR_SLEEPDEEP_Msk); in pm_state_exit_post_ops()
/Zephyr-latest/soc/microchip/mec/mec15xx/
Ddevice_power.c41 SCB->SCR &= ~(1ul << 2); in soc_lite_sleep_enable()
52 SCB->SCR = (1ul << 2); /* Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_enable()
65 SCB->SCR &= ~(1ul << 2); /* disable Cortex-M4 SLEEPDEEP */ in soc_deep_sleep_disable()
/Zephyr-latest/soc/nordic/nrf54h/
Dpm_s2ram.c47 uint32_t SCR; member
132 backup->SCR = SCB->SCR; in scb_suspend()
149 SCB->SCR = backup->SCR; in scb_resume()
/Zephyr-latest/soc/atmel/sam/common/
Dsoc_poweroff.c17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
Dsoc_sam4l_poweroff.c17 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in soc_core_sleepdeep_enable()
/Zephyr-latest/arch/arm/core/cortex_m/
Dcpu_idle.c27 SCB->SCR = SCB_SCR_SEVONPEND_Msk; in z_arm_cpu_idle_init()
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpower.c106 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in lpm_enter_sleep_mode()
109 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in lpm_enter_sleep_mode()
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_uart.h173 volatile uint8_t SCR; member
/Zephyr-latest/soc/nxp/imxrt/imxrt11xx/
Dpower.c240 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; in system_enter_sleep()
243 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; in system_enter_sleep()
Dsoc.c806 SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; in second_core_boot()
/Zephyr-latest/drivers/i2c/
Di2c_sam4l_twim.c298 twim->SCR = ~0UL; /* Clear the status flags */ in i2c_start_xfer()
496 twim->SCR = ~0UL; in i2c_sam_twim_isr()
573 twim->SCR = ~0UL; in i2c_sam_twim_initialize()
/Zephyr-latest/drivers/serial/
Duart_renesas_ra_sci.c363 cfg->regs->SCR |= (R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in uart_ra_sci_irq_tx_enable()
370 cfg->regs->SCR &= ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in uart_ra_sci_irq_tx_disable()
464 scr = cfg->regs->SCR; in uart_ra_sci_irq_is_pending()
475 scr = cfg->regs->SCR; in uart_ra_sci_irq_is_pending()
669 cfg->regs->SCR &= (uint8_t) ~(R_SCI0_SCR_TIE_Msk | R_SCI0_SCR_TEIE_Msk); in disable_tx()
Duart_mchp_xec.c414 regs->SCR = regs->RTXB; in uart_xec_configure()
/Zephyr-latest/drivers/clock_control/
Dclock_control_mchp_xec.c209 SCB->SCR &= ~BIT(2); in pcr_slp_init()
1004 SCB->SCR |= BIT(2); in mchp_xec_clk_ctrl_sys_sleep_enable()
1012 SCB->SCR &= ~BIT(2); in mchp_xec_clk_ctrl_sys_sleep_disable()
/Zephyr-latest/drivers/spi/
Dspi_pl022.c73 #define SSP_CR0_MASK_SCR SSP_MASK(CR0, SCR)