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Searched refs:RSTMGR_WATCHDOG0_RSTLINE (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dintel_socfpga_reset.h102 #define RSTMGR_WATCHDOG0_RSTLINE 320 macro
/Zephyr-latest/dts/arm64/intel/
Dintel_socfpga_agilex5.dtsi185 resets = <&reset RSTMGR_WATCHDOG0_RSTLINE>;