1 /*
2 * Copyright (c) 2010, 2012-2015 Wind River Systems, Inc.
3 * Copyright (c) 2020 Intel Corp.
4 * Copyright (c) 2021 Microchip Technology Inc.
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 /**
10 * @brief Microchip XEC UART Serial Driver
11 *
12 * This is the driver for the Microchip XEC MCU UART. It is NS16550 compatible.
13 *
14 */
15
16 #define DT_DRV_COMPAT microchip_xec_uart
17
18 #include <errno.h>
19 #include <zephyr/kernel.h>
20 #include <zephyr/arch/cpu.h>
21 #include <zephyr/types.h>
22 #include <soc.h>
23
24 #include <zephyr/init.h>
25 #include <zephyr/toolchain.h>
26 #include <zephyr/linker/sections.h>
27 #ifdef CONFIG_SOC_SERIES_MEC172X
28 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
29 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
30 #endif
31 #include <zephyr/drivers/pinctrl.h>
32 #include <zephyr/drivers/uart.h>
33 #include <zephyr/drivers/gpio.h>
34 #include <zephyr/sys/sys_io.h>
35 #include <zephyr/spinlock.h>
36 #include <zephyr/irq.h>
37 #include <zephyr/pm/device.h>
38 #include <zephyr/pm/policy.h>
39
40 #include <zephyr/logging/log.h>
41 LOG_MODULE_REGISTER(uart_xec, CONFIG_UART_LOG_LEVEL);
42
43 /* Clock source is 1.8432 MHz derived from PLL 48 MHz */
44 #define XEC_UART_CLK_SRC_1P8M 0
45 /* Clock source is PLL 48 MHz output */
46 #define XEC_UART_CLK_SRC_48M 1
47 /* Clock source is the UART_CLK alternate pin function. */
48 #define XEC_UART_CLK_SRC_EXT_PIN 2
49
50 /* register definitions */
51
52 #define REG_THR 0x00 /* Transmitter holding reg. */
53 #define REG_RDR 0x00 /* Receiver data reg. */
54 #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
55 #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
56 #define REG_IER 0x01 /* Interrupt enable reg. */
57 #define REG_IIR 0x02 /* Interrupt ID reg. */
58 #define REG_FCR 0x02 /* FIFO control reg. */
59 #define REG_LCR 0x03 /* Line control reg. */
60 #define REG_MDC 0x04 /* Modem control reg. */
61 #define REG_LSR 0x05 /* Line status reg. */
62 #define REG_MSR 0x06 /* Modem status reg. */
63 #define REG_SCR 0x07 /* scratch register */
64 #define REG_LD_ACTV 0x330 /* Logical Device activate */
65 #define REG_LD_CFG 0x3f0 /* Logical Device configuration */
66
67 /* equates for interrupt enable register */
68
69 #define IER_RXRDY 0x01 /* receiver data ready */
70 #define IER_TBE 0x02 /* transmit bit enable */
71 #define IER_LSR 0x04 /* line status interrupts */
72 #define IER_MSI 0x08 /* modem status interrupts */
73
74 /* equates for interrupt identification register */
75
76 #define IIR_MSTAT 0x00 /* modem status interrupt */
77 #define IIR_NIP 0x01 /* no interrupt pending */
78 #define IIR_THRE 0x02 /* transmit holding register empty interrupt */
79 #define IIR_RBRF 0x04 /* receiver buffer register full interrupt */
80 #define IIR_LS 0x06 /* receiver line status interrupt */
81 #define IIR_MASK 0x07 /* interrupt id bits mask */
82 #define IIR_ID 0x06 /* interrupt ID mask without NIP */
83
84 /* equates for FIFO control register */
85
86 #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
87 #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
88 #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
89
90 /*
91 * Per PC16550D (Literature Number: SNLS378B):
92 *
93 * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
94 * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
95 * character in the RCVR FIFO or RCVR holding register, the
96 * RXRDY pin (29) will be low active. Once it is activated the
97 * RXRDY pin will go inactive when there are no more charac-
98 * ters in the FIFO or holding register.
99 *
100 * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
101 * FCR3 = 1 and the trigger level or the timeout has been
102 * reached, the RXRDY pin will go low active. Once it is acti-
103 * vated it will go inactive when there are no more characters
104 * in the FIFO or holding register.
105 *
106 * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
107 * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
108 * ters in the XMIT FIFO or XMIT holding register, the TXRDY
109 * pin (24) will be low active. Once it is activated the TXRDY
110 * pin will go inactive after the first character is loaded into the
111 * XMIT FIFO or holding register.
112 *
113 * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
114 * FCR3 = 1 and there are no characters in the XMIT FIFO, the
115 * TXRDY pin will go low active. This pin will become inactive
116 * when the XMIT FIFO is completely full.
117 */
118 #define FCR_MODE0 0x00 /* set receiver in mode 0 */
119 #define FCR_MODE1 0x08 /* set receiver in mode 1 */
120
121 /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
122 #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
123 #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
124 #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
125 #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
126
127 /* constants for line control register */
128
129 #define LCR_CS5 0x00 /* 5 bits data size */
130 #define LCR_CS6 0x01 /* 6 bits data size */
131 #define LCR_CS7 0x02 /* 7 bits data size */
132 #define LCR_CS8 0x03 /* 8 bits data size */
133 #define LCR_2_STB 0x04 /* 2 stop bits */
134 #define LCR_1_STB 0x00 /* 1 stop bit */
135 #define LCR_PEN 0x08 /* parity enable */
136 #define LCR_PDIS 0x00 /* parity disable */
137 #define LCR_EPS 0x10 /* even parity select */
138 #define LCR_SP 0x20 /* stick parity select */
139 #define LCR_SBRK 0x40 /* break control bit */
140 #define LCR_DLAB 0x80 /* divisor latch access enable */
141
142 /* constants for the modem control register */
143
144 #define MCR_DTR 0x01 /* dtr output */
145 #define MCR_RTS 0x02 /* rts output */
146 #define MCR_OUT1 0x04 /* output #1 */
147 #define MCR_OUT2 0x08 /* output #2 */
148 #define MCR_LOOP 0x10 /* loop back */
149 #define MCR_AFCE 0x20 /* auto flow control enable */
150
151 /* constants for line status register */
152
153 #define LSR_RXRDY 0x01 /* receiver data available */
154 #define LSR_OE 0x02 /* overrun error */
155 #define LSR_PE 0x04 /* parity error */
156 #define LSR_FE 0x08 /* framing error */
157 #define LSR_BI 0x10 /* break interrupt */
158 #define LSR_EOB_MASK 0x1E /* Error or Break mask */
159 #define LSR_THRE 0x20 /* transmit holding register empty */
160 #define LSR_TEMT 0x40 /* transmitter empty */
161
162 /* constants for modem status register */
163
164 #define MSR_DCTS 0x01 /* cts change */
165 #define MSR_DDSR 0x02 /* dsr change */
166 #define MSR_DRI 0x04 /* ring change */
167 #define MSR_DDCD 0x08 /* data carrier change */
168 #define MSR_CTS 0x10 /* complement of cts */
169 #define MSR_DSR 0x20 /* complement of dsr */
170 #define MSR_RI 0x40 /* complement of ring signal */
171 #define MSR_DCD 0x80 /* complement of dcd */
172
173 #define IIRC(dev) (((struct uart_xec_dev_data *)(dev)->data)->iir_cache)
174
175 enum uart_xec_pm_policy_state_flag {
176 UART_XEC_PM_POLICY_STATE_TX_FLAG,
177 UART_XEC_PM_POLICY_STATE_RX_FLAG,
178 UART_XEC_PM_POLICY_STATE_FLAG_COUNT,
179 };
180
181 /* device config */
182 struct uart_xec_device_config {
183 struct uart_regs *regs;
184 uint32_t sys_clk_freq;
185 uint8_t girq_id;
186 uint8_t girq_pos;
187 uint8_t pcr_idx;
188 uint8_t pcr_bitpos;
189 const struct pinctrl_dev_config *pcfg;
190 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
191 uart_irq_config_func_t irq_config_func;
192 #endif
193 #ifdef CONFIG_PM_DEVICE
194 struct gpio_dt_spec wakerx_gpio;
195 bool wakeup_source;
196 #endif
197 };
198
199 /** Device data structure */
200 struct uart_xec_dev_data {
201 struct uart_config uart_config;
202 struct k_spinlock lock;
203
204 uint8_t fcr_cache; /**< cache of FCR write only register */
205 uint8_t iir_cache; /**< cache of IIR since it clears when read */
206 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
207 uart_irq_callback_user_data_t cb; /**< Callback function pointer */
208 void *cb_data; /**< Callback function arg */
209 #endif
210 };
211
212 #ifdef CONFIG_PM_DEVICE
213 ATOMIC_DEFINE(pm_policy_state_flag, UART_XEC_PM_POLICY_STATE_FLAG_COUNT);
214 #endif
215
216 #if defined(CONFIG_PM_DEVICE) && defined(CONFIG_UART_CONSOLE_INPUT_EXPIRED)
217 struct k_work_delayable rx_refresh_timeout_work;
218 #endif
219
220 static DEVICE_API(uart, uart_xec_driver_api);
221
222 #if defined(CONFIG_PM_DEVICE) && defined(CONFIG_UART_CONSOLE_INPUT_EXPIRED)
uart_xec_pm_policy_state_lock_get(enum uart_xec_pm_policy_state_flag flag)223 static void uart_xec_pm_policy_state_lock_get(enum uart_xec_pm_policy_state_flag flag)
224 {
225 if (atomic_test_and_set_bit(pm_policy_state_flag, flag) == 0) {
226 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
227 }
228 }
229
uart_xec_pm_policy_state_lock_put(enum uart_xec_pm_policy_state_flag flag)230 static void uart_xec_pm_policy_state_lock_put(enum uart_xec_pm_policy_state_flag flag)
231 {
232 if (atomic_test_and_clear_bit(pm_policy_state_flag, flag) == 1) {
233 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
234 }
235 }
236 #endif
237
238 #ifdef CONFIG_SOC_SERIES_MEC172X
239
uart_clr_slp_en(const struct device * dev)240 static void uart_clr_slp_en(const struct device *dev)
241 {
242 struct uart_xec_device_config const *dev_cfg = dev->config;
243
244 z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, dev_cfg->pcr_bitpos, 0);
245 }
246
uart_xec_girq_clr(const struct device * dev)247 static inline void uart_xec_girq_clr(const struct device *dev)
248 {
249 struct uart_xec_device_config const *dev_cfg = dev->config;
250
251 mchp_soc_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos);
252 }
253
uart_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)254 static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
255 {
256 mchp_xec_ecia_girq_src_en(girq_idx, girq_posn);
257 }
258
259 #else
260
uart_clr_slp_en(const struct device * dev)261 static void uart_clr_slp_en(const struct device *dev)
262 {
263 struct uart_xec_device_config const *dev_cfg = dev->config;
264
265 if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART0_POS) {
266 mchp_pcr_periph_slp_ctrl(PCR_UART0, 0);
267 } else if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART1_POS) {
268 mchp_pcr_periph_slp_ctrl(PCR_UART1, 0);
269 } else {
270 mchp_pcr_periph_slp_ctrl(PCR_UART2, 0);
271 }
272 }
273
uart_xec_girq_clr(const struct device * dev)274 static inline void uart_xec_girq_clr(const struct device *dev)
275 {
276 struct uart_xec_device_config const *dev_cfg = dev->config;
277
278 MCHP_GIRQ_SRC(dev_cfg->girq_id) = BIT(dev_cfg->girq_pos);
279 }
280
uart_xec_girq_en(uint8_t girq_idx,uint8_t girq_posn)281 static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
282 {
283 MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn);
284 }
285
286 #endif
287
set_baud_rate(const struct device * dev,uint32_t baud_rate)288 static void set_baud_rate(const struct device *dev, uint32_t baud_rate)
289 {
290 const struct uart_xec_device_config * const dev_cfg = dev->config;
291 struct uart_xec_dev_data * const dev_data = dev->data;
292 struct uart_regs *regs = dev_cfg->regs;
293 uint32_t divisor; /* baud rate divisor */
294 uint8_t lcr_cache;
295
296 if ((baud_rate != 0U) && (dev_cfg->sys_clk_freq != 0U)) {
297 /*
298 * calculate baud rate divisor. a variant of
299 * (uint32_t)(dev_cfg->sys_clk_freq / (16.0 * baud_rate) + 0.5)
300 */
301 divisor = ((dev_cfg->sys_clk_freq + (baud_rate << 3))
302 / baud_rate) >> 4;
303
304 /* set the DLAB to access the baud rate divisor registers */
305 lcr_cache = regs->LCR;
306 regs->LCR = LCR_DLAB | lcr_cache;
307 regs->RTXB = (unsigned char)(divisor & 0xff);
308 /* bit[7]=0 1.8MHz clock source, =1 48MHz clock source */
309 regs->IER = (unsigned char)((divisor >> 8) & 0x7f);
310
311 /* restore the DLAB to access the baud rate divisor registers */
312 regs->LCR = lcr_cache;
313
314 dev_data->uart_config.baudrate = baud_rate;
315 }
316 }
317
318 /*
319 * Configure UART.
320 * MCHP XEC UART defaults to reset if external Host VCC_PWRGD is inactive.
321 * We must change the UART reset signal to XEC VTR_PWRGD. Make sure UART
322 * clock source is an internal clock and UART pins are not inverted.
323 */
uart_xec_configure(const struct device * dev,const struct uart_config * cfg)324 static int uart_xec_configure(const struct device *dev,
325 const struct uart_config *cfg)
326 {
327 struct uart_xec_dev_data * const dev_data = dev->data;
328 const struct uart_xec_device_config * const dev_cfg = dev->config;
329 struct uart_regs *regs = dev_cfg->regs;
330 uint8_t lcr_cache;
331
332 /* temp for return value if error occurs in this locked region */
333 int ret = 0;
334
335 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
336
337 ARG_UNUSED(dev_data);
338
339 dev_data->fcr_cache = 0U;
340 dev_data->iir_cache = 0U;
341
342 /* XEC UART specific configuration and enable */
343 regs->CFG_SEL &= ~(MCHP_UART_LD_CFG_RESET_VCC |
344 MCHP_UART_LD_CFG_EXTCLK | MCHP_UART_LD_CFG_INVERT);
345 /* set activate to enable clocks */
346 regs->ACTV |= MCHP_UART_LD_ACTIVATE;
347
348 set_baud_rate(dev, cfg->baudrate);
349
350 /* Local structure to hold temporary values */
351 struct uart_config uart_cfg;
352
353 switch (cfg->data_bits) {
354 case UART_CFG_DATA_BITS_5:
355 uart_cfg.data_bits = LCR_CS5;
356 break;
357 case UART_CFG_DATA_BITS_6:
358 uart_cfg.data_bits = LCR_CS6;
359 break;
360 case UART_CFG_DATA_BITS_7:
361 uart_cfg.data_bits = LCR_CS7;
362 break;
363 case UART_CFG_DATA_BITS_8:
364 uart_cfg.data_bits = LCR_CS8;
365 break;
366 default:
367 ret = -ENOTSUP;
368 goto out;
369 }
370
371 switch (cfg->stop_bits) {
372 case UART_CFG_STOP_BITS_1:
373 uart_cfg.stop_bits = LCR_1_STB;
374 break;
375 case UART_CFG_STOP_BITS_2:
376 uart_cfg.stop_bits = LCR_2_STB;
377 break;
378 default:
379 ret = -ENOTSUP;
380 goto out;
381 }
382
383 switch (cfg->parity) {
384 case UART_CFG_PARITY_NONE:
385 uart_cfg.parity = LCR_PDIS;
386 break;
387 case UART_CFG_PARITY_EVEN:
388 uart_cfg.parity = LCR_EPS;
389 break;
390 default:
391 ret = -ENOTSUP;
392 goto out;
393 }
394
395 dev_data->uart_config = *cfg;
396
397 /* data bits, stop bits, parity, clear DLAB */
398 regs->LCR = uart_cfg.data_bits | uart_cfg.stop_bits | uart_cfg.parity;
399
400 regs->MCR = MCR_OUT2 | MCR_RTS | MCR_DTR;
401
402 /*
403 * Program FIFO: enabled, mode 0
404 * generate the interrupt at 8th byte
405 * Clear TX and RX FIFO
406 */
407 dev_data->fcr_cache = FCR_FIFO | FCR_MODE0 | FCR_FIFO_8 | FCR_RCVRCLR |
408 FCR_XMITCLR;
409 regs->IIR_FCR = dev_data->fcr_cache;
410
411 /* clear the port */
412 lcr_cache = regs->LCR;
413 regs->LCR = LCR_DLAB | lcr_cache;
414 regs->SCR = regs->RTXB;
415 regs->LCR = lcr_cache;
416
417 /* disable interrupts */
418 regs->IER = 0;
419
420 out:
421 k_spin_unlock(&dev_data->lock, key);
422 return ret;
423 };
424
425 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_xec_config_get(const struct device * dev,struct uart_config * cfg)426 static int uart_xec_config_get(const struct device *dev,
427 struct uart_config *cfg)
428 {
429 struct uart_xec_dev_data *data = dev->data;
430
431 cfg->baudrate = data->uart_config.baudrate;
432 cfg->parity = data->uart_config.parity;
433 cfg->stop_bits = data->uart_config.stop_bits;
434 cfg->data_bits = data->uart_config.data_bits;
435 cfg->flow_ctrl = data->uart_config.flow_ctrl;
436
437 return 0;
438 }
439 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
440
441 #ifdef CONFIG_PM_DEVICE
442
uart_xec_wake_handler(const struct device * gpio,struct gpio_callback * cb,uint32_t pins)443 static void uart_xec_wake_handler(const struct device *gpio, struct gpio_callback *cb,
444 uint32_t pins)
445 {
446 /* Disable interrupts on UART RX pin to avoid repeated interrupts. */
447 (void)gpio_pin_interrupt_configure(gpio, (find_msb_set(pins) - 1),
448 GPIO_INT_DISABLE);
449 /* Refresh console expired time */
450 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
451 k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
452
453 uart_xec_pm_policy_state_lock_get(UART_XEC_PM_POLICY_STATE_RX_FLAG);
454 k_work_reschedule(&rx_refresh_timeout_work, delay);
455 #endif
456 }
457
uart_xec_pm_action(const struct device * dev,enum pm_device_action action)458 static int uart_xec_pm_action(const struct device *dev,
459 enum pm_device_action action)
460 {
461 const struct uart_xec_device_config * const dev_cfg = dev->config;
462 struct uart_regs *regs = dev_cfg->regs;
463 int ret = 0;
464
465 switch (action) {
466 case PM_DEVICE_ACTION_RESUME:
467 regs->ACTV = MCHP_UART_LD_ACTIVATE;
468 break;
469 case PM_DEVICE_ACTION_SUSPEND:
470 /* Enable UART wake interrupt */
471 regs->ACTV = 0;
472 if ((dev_cfg->wakeup_source) && (dev_cfg->wakerx_gpio.port != NULL)) {
473 ret = gpio_pin_interrupt_configure_dt(&dev_cfg->wakerx_gpio,
474 GPIO_INT_MODE_EDGE | GPIO_INT_TRIG_LOW);
475 if (ret < 0) {
476 LOG_ERR("Failed to configure UART wake interrupt (ret %d)", ret);
477 return ret;
478 }
479 }
480 break;
481 default:
482 return -ENOTSUP;
483 }
484
485 return 0;
486 }
487
488 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
uart_xec_rx_refresh_timeout(struct k_work * work)489 static void uart_xec_rx_refresh_timeout(struct k_work *work)
490 {
491 ARG_UNUSED(work);
492
493 uart_xec_pm_policy_state_lock_put(UART_XEC_PM_POLICY_STATE_RX_FLAG);
494 }
495 #endif
496 #endif /* CONFIG_PM_DEVICE */
497
498 /**
499 * @brief Initialize individual UART port
500 *
501 * This routine is called to reset the chip in a quiescent state.
502 *
503 * @param dev UART device struct
504 *
505 * @return 0 if successful, failed otherwise
506 */
uart_xec_init(const struct device * dev)507 static int uart_xec_init(const struct device *dev)
508 {
509 const struct uart_xec_device_config * const dev_cfg = dev->config;
510 struct uart_xec_dev_data *dev_data = dev->data;
511 int ret;
512
513 uart_clr_slp_en(dev);
514
515 ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
516 if (ret != 0) {
517 return ret;
518 }
519
520 ret = uart_xec_configure(dev, &dev_data->uart_config);
521 if (ret != 0) {
522 return ret;
523 }
524
525 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
526 dev_cfg->irq_config_func(dev);
527 #endif
528
529 #ifdef CONFIG_PM_DEVICE
530 #ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
531 k_work_init_delayable(&rx_refresh_timeout_work, uart_xec_rx_refresh_timeout);
532 #endif
533 if ((dev_cfg->wakeup_source) && (dev_cfg->wakerx_gpio.port != NULL)) {
534 static struct gpio_callback uart_xec_wake_cb;
535
536 gpio_init_callback(&uart_xec_wake_cb, uart_xec_wake_handler,
537 BIT(dev_cfg->wakerx_gpio.pin));
538
539 ret = gpio_add_callback(dev_cfg->wakerx_gpio.port, &uart_xec_wake_cb);
540 if (ret < 0) {
541 LOG_ERR("Failed to add UART wake callback (err %d)", ret);
542 return ret;
543 }
544 }
545 #endif
546
547 return 0;
548 }
549
550 /**
551 * @brief Poll the device for input.
552 *
553 * @param dev UART device struct
554 * @param c Pointer to character
555 *
556 * @return 0 if a character arrived, -1 if the input buffer if empty.
557 */
uart_xec_poll_in(const struct device * dev,unsigned char * c)558 static int uart_xec_poll_in(const struct device *dev, unsigned char *c)
559 {
560 const struct uart_xec_device_config * const dev_cfg = dev->config;
561 struct uart_xec_dev_data *dev_data = dev->data;
562 struct uart_regs *regs = dev_cfg->regs;
563 int ret = -1;
564 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
565
566 if ((regs->LSR & LSR_RXRDY) != 0) {
567 /* got a character */
568 *c = regs->RTXB;
569 ret = 0;
570 }
571
572 k_spin_unlock(&dev_data->lock, key);
573
574 return ret;
575 }
576
577 /**
578 * @brief Output a character in polled mode.
579 *
580 * Checks if the transmitter is empty. If empty, a character is written to
581 * the data register.
582 *
583 * If the hardware flow control is enabled then the handshake signal CTS has to
584 * be asserted in order to send a character.
585 *
586 * @param dev UART device struct
587 * @param c Character to send
588 */
uart_xec_poll_out(const struct device * dev,unsigned char c)589 static void uart_xec_poll_out(const struct device *dev, unsigned char c)
590 {
591 const struct uart_xec_device_config * const dev_cfg = dev->config;
592 struct uart_xec_dev_data *dev_data = dev->data;
593 struct uart_regs *regs = dev_cfg->regs;
594 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
595
596 while ((regs->LSR & LSR_THRE) == 0) {
597 ;
598 }
599
600 regs->RTXB = c;
601
602 k_spin_unlock(&dev_data->lock, key);
603 }
604
605 /**
606 * @brief Check if an error was received
607 *
608 * @param dev UART device struct
609 *
610 * @return one of UART_ERROR_OVERRUN, UART_ERROR_PARITY, UART_ERROR_FRAMING,
611 * UART_BREAK if an error was detected, 0 otherwise.
612 */
uart_xec_err_check(const struct device * dev)613 static int uart_xec_err_check(const struct device *dev)
614 {
615 const struct uart_xec_device_config * const dev_cfg = dev->config;
616 struct uart_xec_dev_data *dev_data = dev->data;
617 struct uart_regs *regs = dev_cfg->regs;
618 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
619 int check = regs->LSR & LSR_EOB_MASK;
620
621 k_spin_unlock(&dev_data->lock, key);
622
623 return check >> 1;
624 }
625
626 #if CONFIG_UART_INTERRUPT_DRIVEN
627
628 /**
629 * @brief Fill FIFO with data
630 *
631 * @param dev UART device struct
632 * @param tx_data Data to transmit
633 * @param size Number of bytes to send
634 *
635 * @return Number of bytes sent
636 */
uart_xec_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)637 static int uart_xec_fifo_fill(const struct device *dev, const uint8_t *tx_data,
638 int size)
639 {
640 const struct uart_xec_device_config * const dev_cfg = dev->config;
641 struct uart_xec_dev_data *dev_data = dev->data;
642 struct uart_regs *regs = dev_cfg->regs;
643 int i;
644 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
645
646 for (i = 0; (i < size) && (regs->LSR & LSR_THRE) != 0; i++) {
647 #if defined(CONFIG_PM_DEVICE) && defined(CONFIG_UART_CONSOLE_INPUT_EXPIRED)
648 uart_xec_pm_policy_state_lock_get(UART_XEC_PM_POLICY_STATE_TX_FLAG);
649 #endif
650 regs->RTXB = tx_data[i];
651 }
652
653 k_spin_unlock(&dev_data->lock, key);
654
655 return i;
656 }
657
658 /**
659 * @brief Read data from FIFO
660 *
661 * @param dev UART device struct
662 * @param rxData Data container
663 * @param size Container size
664 *
665 * @return Number of bytes read
666 */
uart_xec_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)667 static int uart_xec_fifo_read(const struct device *dev, uint8_t *rx_data,
668 const int size)
669 {
670 const struct uart_xec_device_config * const dev_cfg = dev->config;
671 struct uart_xec_dev_data *dev_data = dev->data;
672 struct uart_regs *regs = dev_cfg->regs;
673 int i;
674 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
675
676 for (i = 0; (i < size) && (regs->LSR & LSR_RXRDY) != 0; i++) {
677 rx_data[i] = regs->RTXB;
678 }
679
680 k_spin_unlock(&dev_data->lock, key);
681
682 return i;
683 }
684
685 /**
686 * @brief Enable TX interrupt in IER
687 *
688 * @param dev UART device struct
689 */
uart_xec_irq_tx_enable(const struct device * dev)690 static void uart_xec_irq_tx_enable(const struct device *dev)
691 {
692 const struct uart_xec_device_config * const dev_cfg = dev->config;
693 struct uart_xec_dev_data *dev_data = dev->data;
694 struct uart_regs *regs = dev_cfg->regs;
695 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
696
697 regs->IER |= IER_TBE;
698
699 k_spin_unlock(&dev_data->lock, key);
700 }
701
702 /**
703 * @brief Disable TX interrupt in IER
704 *
705 * @param dev UART device struct
706 */
uart_xec_irq_tx_disable(const struct device * dev)707 static void uart_xec_irq_tx_disable(const struct device *dev)
708 {
709 const struct uart_xec_device_config * const dev_cfg = dev->config;
710 struct uart_xec_dev_data *dev_data = dev->data;
711 struct uart_regs *regs = dev_cfg->regs;
712 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
713
714 regs->IER &= ~(IER_TBE);
715
716 k_spin_unlock(&dev_data->lock, key);
717 }
718
719 /**
720 * @brief Check if Tx IRQ has been raised
721 *
722 * @param dev UART device struct
723 *
724 * @return 1 if an IRQ is ready, 0 otherwise
725 */
uart_xec_irq_tx_ready(const struct device * dev)726 static int uart_xec_irq_tx_ready(const struct device *dev)
727 {
728 struct uart_xec_dev_data *dev_data = dev->data;
729 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
730
731 int ret = ((IIRC(dev) & IIR_ID) == IIR_THRE) ? 1 : 0;
732
733 k_spin_unlock(&dev_data->lock, key);
734
735 return ret;
736 }
737
738 /**
739 * @brief Check if nothing remains to be transmitted
740 *
741 * @param dev UART device struct
742 *
743 * @return 1 if nothing remains to be transmitted, 0 otherwise
744 */
uart_xec_irq_tx_complete(const struct device * dev)745 static int uart_xec_irq_tx_complete(const struct device *dev)
746 {
747 const struct uart_xec_device_config * const dev_cfg = dev->config;
748 struct uart_xec_dev_data *dev_data = dev->data;
749 struct uart_regs *regs = dev_cfg->regs;
750 int ret;
751 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
752
753 if ((regs->IER & IER_TBE) ||
754 ((regs->LSR & (LSR_TEMT | LSR_THRE)) != (LSR_TEMT | LSR_THRE))) {
755 ret = 0;
756 } else {
757 ret = 1;
758 }
759
760 k_spin_unlock(&dev_data->lock, key);
761
762 return ret;
763 }
764
765 /**
766 * @brief Enable RX interrupt in IER
767 *
768 * @param dev UART device struct
769 */
uart_xec_irq_rx_enable(const struct device * dev)770 static void uart_xec_irq_rx_enable(const struct device *dev)
771 {
772 const struct uart_xec_device_config * const dev_cfg = dev->config;
773 struct uart_xec_dev_data *dev_data = dev->data;
774 struct uart_regs *regs = dev_cfg->regs;
775 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
776
777 regs->IER |= IER_RXRDY;
778
779 k_spin_unlock(&dev_data->lock, key);
780 }
781
782 /**
783 * @brief Disable RX interrupt in IER
784 *
785 * @param dev UART device struct
786 */
uart_xec_irq_rx_disable(const struct device * dev)787 static void uart_xec_irq_rx_disable(const struct device *dev)
788 {
789 const struct uart_xec_device_config * const dev_cfg = dev->config;
790 struct uart_xec_dev_data *dev_data = dev->data;
791 struct uart_regs *regs = dev_cfg->regs;
792 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
793
794 regs->IER &= ~(IER_RXRDY);
795
796 k_spin_unlock(&dev_data->lock, key);
797 }
798
799 /**
800 * @brief Check if Rx IRQ has been raised
801 *
802 * @param dev UART device struct
803 *
804 * @return 1 if an IRQ is ready, 0 otherwise
805 */
uart_xec_irq_rx_ready(const struct device * dev)806 static int uart_xec_irq_rx_ready(const struct device *dev)
807 {
808 struct uart_xec_dev_data *dev_data = dev->data;
809 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
810
811 int ret = ((IIRC(dev) & IIR_ID) == IIR_RBRF) ? 1 : 0;
812
813 k_spin_unlock(&dev_data->lock, key);
814
815 return ret;
816 }
817
818 /**
819 * @brief Enable error interrupt in IER
820 *
821 * @param dev UART device struct
822 */
uart_xec_irq_err_enable(const struct device * dev)823 static void uart_xec_irq_err_enable(const struct device *dev)
824 {
825 const struct uart_xec_device_config * const dev_cfg = dev->config;
826 struct uart_xec_dev_data *dev_data = dev->data;
827 struct uart_regs *regs = dev_cfg->regs;
828 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
829
830 regs->IER |= IER_LSR;
831
832 k_spin_unlock(&dev_data->lock, key);
833 }
834
835 /**
836 * @brief Disable error interrupt in IER
837 *
838 * @param dev UART device struct
839 *
840 * @return 1 if an IRQ is ready, 0 otherwise
841 */
uart_xec_irq_err_disable(const struct device * dev)842 static void uart_xec_irq_err_disable(const struct device *dev)
843 {
844 const struct uart_xec_device_config * const dev_cfg = dev->config;
845 struct uart_xec_dev_data *dev_data = dev->data;
846 struct uart_regs *regs = dev_cfg->regs;
847 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
848
849 regs->IER &= ~(IER_LSR);
850
851 k_spin_unlock(&dev_data->lock, key);
852 }
853
854 /**
855 * @brief Check if any IRQ is pending
856 *
857 * @param dev UART device struct
858 *
859 * @return 1 if an IRQ is pending, 0 otherwise
860 */
uart_xec_irq_is_pending(const struct device * dev)861 static int uart_xec_irq_is_pending(const struct device *dev)
862 {
863 struct uart_xec_dev_data *dev_data = dev->data;
864 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
865
866 int ret = (!(IIRC(dev) & IIR_NIP)) ? 1 : 0;
867
868 k_spin_unlock(&dev_data->lock, key);
869
870 return ret;
871 }
872
873 /**
874 * @brief Update cached contents of IIR
875 *
876 * @param dev UART device struct
877 *
878 * @return Always 1
879 */
uart_xec_irq_update(const struct device * dev)880 static int uart_xec_irq_update(const struct device *dev)
881 {
882 const struct uart_xec_device_config * const dev_cfg = dev->config;
883 struct uart_xec_dev_data *dev_data = dev->data;
884 struct uart_regs *regs = dev_cfg->regs;
885 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
886
887 IIRC(dev) = regs->IIR_FCR;
888
889 k_spin_unlock(&dev_data->lock, key);
890
891 return 1;
892 }
893
894 /**
895 * @brief Set the callback function pointer for IRQ.
896 *
897 * @param dev UART device struct
898 * @param cb Callback function pointer.
899 */
uart_xec_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)900 static void uart_xec_irq_callback_set(const struct device *dev,
901 uart_irq_callback_user_data_t cb,
902 void *cb_data)
903 {
904 struct uart_xec_dev_data * const dev_data = dev->data;
905 k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
906
907 dev_data->cb = cb;
908 dev_data->cb_data = cb_data;
909
910 k_spin_unlock(&dev_data->lock, key);
911 }
912
913 /**
914 * @brief Interrupt service routine.
915 *
916 * This simply calls the callback function, if one exists.
917 *
918 * @param arg Argument to ISR.
919 */
uart_xec_isr(const struct device * dev)920 static void uart_xec_isr(const struct device *dev)
921 {
922 struct uart_xec_dev_data * const dev_data = dev->data;
923 #if defined(CONFIG_PM_DEVICE) && defined(CONFIG_UART_CONSOLE_INPUT_EXPIRED)
924 const struct uart_xec_device_config * const dev_cfg = dev->config;
925 struct uart_regs *regs = dev_cfg->regs;
926 int rx_ready = 0;
927
928 rx_ready = ((regs->LSR & LSR_RXRDY) == LSR_RXRDY) ? 1 : 0;
929 if (rx_ready) {
930 k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
931
932 uart_xec_pm_policy_state_lock_get(UART_XEC_PM_POLICY_STATE_RX_FLAG);
933 k_work_reschedule(&rx_refresh_timeout_work, delay);
934 }
935 #endif
936
937 if (dev_data->cb) {
938 dev_data->cb(dev, dev_data->cb_data);
939 }
940
941 #if defined(CONFIG_PM_DEVICE) && defined(CONFIG_UART_CONSOLE_INPUT_EXPIRED)
942 if (uart_xec_irq_tx_complete(dev)) {
943 uart_xec_pm_policy_state_lock_put(UART_XEC_PM_POLICY_STATE_TX_FLAG);
944 }
945 #endif /* CONFIG_PM */
946
947 /* clear ECIA GIRQ R/W1C status bit after UART status cleared */
948 uart_xec_girq_clr(dev);
949 }
950
951 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
952
953 #ifdef CONFIG_UART_XEC_LINE_CTRL
954
955 /**
956 * @brief Manipulate line control for UART.
957 *
958 * @param dev UART device struct
959 * @param ctrl The line control to be manipulated
960 * @param val Value to set the line control
961 *
962 * @return 0 if successful, failed otherwise
963 */
uart_xec_line_ctrl_set(const struct device * dev,uint32_t ctrl,uint32_t val)964 static int uart_xec_line_ctrl_set(const struct device *dev,
965 uint32_t ctrl, uint32_t val)
966 {
967 const struct uart_xec_device_config * const dev_cfg = dev->config;
968 struct uart_xec_dev_data *dev_data = dev->data;
969 struct uart_regs *regs = dev_cfg->regs;
970 uint32_t mdc, chg;
971 k_spinlock_key_t key;
972
973 switch (ctrl) {
974 case UART_LINE_CTRL_BAUD_RATE:
975 set_baud_rate(dev, val);
976 return 0;
977
978 case UART_LINE_CTRL_RTS:
979 case UART_LINE_CTRL_DTR:
980 key = k_spin_lock(&dev_data->lock);
981 mdc = regs->MCR;
982
983 if (ctrl == UART_LINE_CTRL_RTS) {
984 chg = MCR_RTS;
985 } else {
986 chg = MCR_DTR;
987 }
988
989 if (val) {
990 mdc |= chg;
991 } else {
992 mdc &= ~(chg);
993 }
994 regs->MCR = mdc;
995 k_spin_unlock(&dev_data->lock, key);
996 return 0;
997 }
998
999 return -ENOTSUP;
1000 }
1001
1002 #endif /* CONFIG_UART_XEC_LINE_CTRL */
1003
1004 static DEVICE_API(uart, uart_xec_driver_api) = {
1005 .poll_in = uart_xec_poll_in,
1006 .poll_out = uart_xec_poll_out,
1007 .err_check = uart_xec_err_check,
1008 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
1009 .configure = uart_xec_configure,
1010 .config_get = uart_xec_config_get,
1011 #endif
1012 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1013
1014 .fifo_fill = uart_xec_fifo_fill,
1015 .fifo_read = uart_xec_fifo_read,
1016 .irq_tx_enable = uart_xec_irq_tx_enable,
1017 .irq_tx_disable = uart_xec_irq_tx_disable,
1018 .irq_tx_ready = uart_xec_irq_tx_ready,
1019 .irq_tx_complete = uart_xec_irq_tx_complete,
1020 .irq_rx_enable = uart_xec_irq_rx_enable,
1021 .irq_rx_disable = uart_xec_irq_rx_disable,
1022 .irq_rx_ready = uart_xec_irq_rx_ready,
1023 .irq_err_enable = uart_xec_irq_err_enable,
1024 .irq_err_disable = uart_xec_irq_err_disable,
1025 .irq_is_pending = uart_xec_irq_is_pending,
1026 .irq_update = uart_xec_irq_update,
1027 .irq_callback_set = uart_xec_irq_callback_set,
1028
1029 #endif
1030
1031 #ifdef CONFIG_UART_XEC_LINE_CTRL
1032 .line_ctrl_set = uart_xec_line_ctrl_set,
1033 #endif
1034 };
1035
1036 #define DEV_CONFIG_REG_INIT(n) \
1037 .regs = (struct uart_regs *)(DT_INST_REG_ADDR(n)),
1038
1039 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
1040 #define DEV_CONFIG_IRQ_FUNC_INIT(n) \
1041 .irq_config_func = irq_config_func##n,
1042 #define UART_XEC_IRQ_FUNC_DECLARE(n) \
1043 static void irq_config_func##n(const struct device *dev);
1044 #define UART_XEC_IRQ_FUNC_DEFINE(n) \
1045 static void irq_config_func##n(const struct device *dev) \
1046 { \
1047 ARG_UNUSED(dev); \
1048 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), \
1049 uart_xec_isr, DEVICE_DT_INST_GET(n), \
1050 0); \
1051 irq_enable(DT_INST_IRQN(n)); \
1052 uart_xec_girq_en(DT_INST_PROP_BY_IDX(n, girqs, 0), \
1053 DT_INST_PROP_BY_IDX(n, girqs, 1)); \
1054 }
1055 #else
1056 /* !CONFIG_UART_INTERRUPT_DRIVEN */
1057 #define DEV_CONFIG_IRQ_FUNC_INIT(n)
1058 #define UART_XEC_IRQ_FUNC_DECLARE(n)
1059 #define UART_XEC_IRQ_FUNC_DEFINE(n)
1060 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
1061
1062 #define DEV_DATA_FLOW_CTRL(n) \
1063 DT_INST_PROP_OR(n, hw_flow_control, UART_CFG_FLOW_CTRL_NONE)
1064
1065 /* To enable wakeup on the UART, the DTS needs to have two entries defined
1066 * in the corresponding UART node in the DTS specifying it as a wake source
1067 * and specifying the UART_RX GPIO; example as below
1068 *
1069 * wakerx-gpios = <&gpio_140_176 25 GPIO_ACTIVE_HIGH>;
1070 * wakeup-source;
1071 */
1072 #ifdef CONFIG_PM_DEVICE
1073 #define XEC_UART_PM_WAKEUP(n) \
1074 .wakeup_source = (uint8_t)DT_INST_PROP_OR(n, wakeup_source, 0), \
1075 .wakerx_gpio = GPIO_DT_SPEC_INST_GET_OR(n, wakerx_gpios, {0}),
1076 #else
1077 #define XEC_UART_PM_WAKEUP(index) /* Not used */
1078 #endif
1079
1080 #define UART_XEC_DEVICE_INIT(n) \
1081 \
1082 PINCTRL_DT_INST_DEFINE(n); \
1083 \
1084 UART_XEC_IRQ_FUNC_DECLARE(n); \
1085 \
1086 static const struct uart_xec_device_config uart_xec_dev_cfg_##n = { \
1087 DEV_CONFIG_REG_INIT(n) \
1088 .sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
1089 .girq_id = DT_INST_PROP_BY_IDX(n, girqs, 0), \
1090 .girq_pos = DT_INST_PROP_BY_IDX(n, girqs, 1), \
1091 .pcr_idx = DT_INST_PROP_BY_IDX(n, pcrs, 0), \
1092 .pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1), \
1093 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
1094 XEC_UART_PM_WAKEUP(n) \
1095 DEV_CONFIG_IRQ_FUNC_INIT(n) \
1096 }; \
1097 static struct uart_xec_dev_data uart_xec_dev_data_##n = { \
1098 .uart_config.baudrate = DT_INST_PROP_OR(n, current_speed, 0), \
1099 .uart_config.parity = UART_CFG_PARITY_NONE, \
1100 .uart_config.stop_bits = UART_CFG_STOP_BITS_1, \
1101 .uart_config.data_bits = UART_CFG_DATA_BITS_8, \
1102 .uart_config.flow_ctrl = DEV_DATA_FLOW_CTRL(n), \
1103 }; \
1104 PM_DEVICE_DT_INST_DEFINE(n, uart_xec_pm_action); \
1105 DEVICE_DT_INST_DEFINE(n, uart_xec_init, \
1106 PM_DEVICE_DT_INST_GET(n), \
1107 &uart_xec_dev_data_##n, \
1108 &uart_xec_dev_cfg_##n, \
1109 PRE_KERNEL_1, \
1110 CONFIG_SERIAL_INIT_PRIORITY, \
1111 &uart_xec_driver_api); \
1112 UART_XEC_IRQ_FUNC_DEFINE(n)
1113
1114 DT_INST_FOREACH_STATUS_OKAY(UART_XEC_DEVICE_INIT)
1115
