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Searched refs:P_RW_U_NA_Msk (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/include/zephyr/arch/arm/mpu/
Darm_mpu_v8.h46 #define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) macro
187 P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
212 P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
241 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
262 P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
271 P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
301 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* Cache-ability */ \
339 {(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
364 case P_RW_U_NA_Msk: \
392 {(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
Darm_mpu_v7m.h25 #define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) macro
127 IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \
132 MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
147 P_RW_U_NA_Msk) }
148 #define REGION_IO_ATTR(size) { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) }
168 #define _K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA_Msk | NOT_EXEC)
231 case P_RW_U_NA_Msk: \
/Zephyr-latest/include/zephyr/arch/arm64/cortex_r/
Darm_mpu.h41 #define P_RW_U_NA_Msk ((P_RW_U_NA << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) macro
138 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
146 .rbar = NOT_EXEC | P_RW_U_NA_Msk | OUTER_SHAREABLE_Msk, \
154 .rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
233 {(P_RW_U_NA_Msk), MPU_MAIR_INDEX_SRAM})
/Zephyr-latest/soc/xlnx/zynqmp/
Darm_mpu_regions.c27 .rasr = (P_RW_U_NA_Msk \
35 .rasr = (P_RW_U_NA_Msk \
/Zephyr-latest/soc/renode/cortex_r8_virtual/
Darm_mpu_regions.c28 .rasr = (P_RW_U_NA_Msk \
36 .rasr = (P_RW_U_NA_Msk \
/Zephyr-latest/soc/st/stm32/stm32h7x/
Dmpu_regions.c22 MPU_RASR_XN_Msk | P_RW_U_NA_Msk) }),