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Searched refs:PRCI_REG (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c36 PRCI_REG(PRCI_COREPLLCFG) = in soc_early_init_hook()
43 while ((PRCI_REG(PRCI_COREPLLCFG) & PLL_LOCK(1)) == 0) { in soc_early_init_hook()
48 PRCI_REG(PRCI_COREPLLSEL) = COREPLLSEL_SEL(COREPLLSEL_COREPLL); in soc_early_init_hook()
49 PRCI_REG(PRCI_CORECLKSEL) = CLKSEL_SEL(CLKSEL_PLL); in soc_early_init_hook()
51 PRCI_REG(PRCI_HFPCLKPLLCFG) = in soc_early_init_hook()
58 while ((PRCI_REG(PRCI_HFPCLKPLLCFG) & PLL_LOCK(1)) == 0) { in soc_early_init_hook()
63 PRCI_REG(PRCI_HFPCLKPLLOUTDIV) = OUTDIV_PLLCKE(OUTDIV_PLLCKE_ENA); in soc_early_init_hook()
64 PRCI_REG(PRCI_HFPCLKPLLSEL) = CLKSEL_SEL(CLKSEL_PLL); in soc_early_init_hook()
66 PRCI_REG(PRCI_DDRPLLCFG) = in soc_early_init_hook()
73 while ((PRCI_REG(PRCI_DDRPLLCFG) & PLL_LOCK(1)) == 0) { in soc_early_init_hook()
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Dprci.h14 #define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset) macro
/Zephyr-latest/soc/sifive/sifive_freedom/fe300/
Dclock.c54 PRCI_REG(PRCI_PLLCFG) = prci; in soc_early_init_hook()
55 PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0)); in soc_early_init_hook()
56 PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1); in soc_early_init_hook()
57 PRCI_REG(PRCI_HFROSCCFG) &= ~ROSC_EN(1); in soc_early_init_hook()
Dprci.h14 #define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset) macro
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dclock.c24 PRCI_REG(PRCI_COREPLLCFG0) = in soc_early_init_hook()
31 while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0) { in soc_early_init_hook()
36 PRCI_REG(PRCI_CORECLKSEL) = CORECLKSEL_CORECLKSEL(CORECLKSEL_CORE_PLL); in soc_early_init_hook()
Dprci.h14 #define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset) macro