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Searched refs:PLL_RANGE_18MHZ (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
55 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
70 PLL_RANGE(PLL_RANGE_18MHZ) | in soc_early_init_hook()
Dprci.h44 #define PLL_RANGE_18MHZ 3 macro