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Searched refs:PLL_RANGE (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/soc/sifive/sifive_freedom/fu700/
Dclock.c40 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
55 PLL_RANGE(PLL_RANGE_18MHZ) | /* 18MHz <= post divr(= 26MHz) < 30MHz */ in soc_early_init_hook()
70 PLL_RANGE(PLL_RANGE_18MHZ) | in soc_early_init_hook()
Dprci.h36 #define PLL_RANGE(x) (((x) & 0x7) << 18) macro
/Zephyr-latest/soc/sifive/sifive_freedom/fu500/
Dclock.c28 PLL_RANGE(PLL_RANGE_33MHZ) | in soc_early_init_hook()
Dprci.h30 #define PLL_RANGE(x) (((x) & 0x7) << 18) macro