Searched refs:PLL_R (Results 1 – 7 of 7) sorted by relevance
37 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()52 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()67 PLL_R(0) | /* input divider: Fin / (0 + 1) = 26MHz */ in soc_early_init_hook()
33 #define PLL_R(x) (((x) & 0x3f) << 0) macro
25 PLL_R(0) | /* input divider: Fin / (0 + 1) = 33.33MHz */ in soc_early_init_hook()
27 #define PLL_R(x) (((x) & 0x3f) << 0) macro
51 prci = PLL_REFSEL(1) | PLL_R(pll_r) | PLL_F(pll_f) | PLL_Q(pll_q); in soc_early_init_hook()
33 #define PLL_R(x) (((x) & 0x7) << 0) macro
525 * STM32: PLL_P, PLL_Q, PLL_R outputs can now be used as domain clock.
