Searched refs:PLL_Q (Results 1 – 9 of 9) sorted by relevance
39 PLL_Q(2) | /* output divider: VCO / 2^2 = 1001MHz */ in soc_early_init_hook()54 PLL_Q(4) | /* output divider: VCO / 2^4 = 250.25MHz */ in soc_early_init_hook()69 PLL_Q(2) | /* output divider: VCO / 2^2 = 936MHz */ in soc_early_init_hook()
35 #define PLL_Q(x) (((x) & 0x7) << 15) macro
27 PLL_Q(2) | /* output divider: VCO / 2^2 = 999.9MHz */ in soc_early_init_hook()
29 #define PLL_Q(x) (((x) & 0x7) << 15) macro
51 prci = PLL_REFSEL(1) | PLL_R(pll_r) | PLL_F(pll_f) | PLL_Q(pll_q); in soc_early_init_hook()
36 #define PLL_Q(x) (((x) & 0x3) << 10) macro
13 * APB2 and PLL_Q clock frequencies are equal.
525 * STM32: PLL_P, PLL_Q, PLL_R outputs can now be used as domain clock.2278 * :github:`47101` - drivers: clock_control: stm32 common: PLL_Q divider not converted to reg val
576 and configured as domain clock for these devices, otherwise PLL_Q output or MSI is used.
