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Searched refs:PLL3_ID (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c40 #define PLL3_ID 3 macro
54 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
58 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
62 (IS_ENABLED(STM32_PLL3_SRC_CSI) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
324 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
330 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
336 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
576 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls()
Dclock_stm32_ll_u5.c37 #define PLL3_ID 3 macro
59 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
63 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
67 (IS_ENABLED(STM32_PLL3_SRC_MSIS) && pll_id == PLL3_ID)) { in get_pllsrc_frequency()
340 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
346 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
352 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL3_ID), in stm32_clock_control_get_subsys_rate()
661 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range, PLL3_ID); in set_up_plls()
Dclock_stm32_ll_n6.c43 #define PLL3_ID 3 macro
58 (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID) || in get_pllsrc_frequency()
63 (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID) || in get_pllsrc_frequency()
98 case PLL3_ID: in get_pllout_frequency()
130 return get_pllout_frequency(PLL3_ID) / div; in get_icout_frequency()
329 *rate = get_pllout_frequency(PLL3_ID); in stm32_clock_control_get_subsys_rate()