Searched refs:PLL2_ID (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_h5.c | 39 #define PLL2_ID 2 macro
53 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
57 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
61 (IS_ENABLED(STM32_PLL2_SRC_CSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
303 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
309 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
315 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
517 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
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| D | clock_stm32_ll_u5.c | 36 #define PLL2_ID 2 macro
58 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
62 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
66 (IS_ENABLED(STM32_PLL2_SRC_MSIS) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
318 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
324 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
330 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
607 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
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