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Searched refs:PLL2_ID (Results 1 – 3 of 3) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c39 #define PLL2_ID 2 macro
53 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
57 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
61 (IS_ENABLED(STM32_PLL2_SRC_CSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
304 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
310 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
316 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
522 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
Dclock_stm32_ll_u5.c36 #define PLL2_ID 2 macro
58 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
62 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
66 (IS_ENABLED(STM32_PLL2_SRC_MSIS) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
320 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
326 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
332 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL2_ID), in stm32_clock_control_get_subsys_rate()
609 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range, PLL2_ID); in set_up_plls()
Dclock_stm32_ll_n6.c42 #define PLL2_ID 2 macro
57 (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
62 (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) || in get_pllsrc_frequency()
90 case PLL2_ID: in get_pllout_frequency()
128 return get_pllout_frequency(PLL2_ID) / div; in get_icout_frequency()
326 *rate = get_pllout_frequency(PLL2_ID); in stm32_clock_control_get_subsys_rate()