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Searched refs:PLL1_ID (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_h5.c38 #define PLL1_ID 1 macro
52 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
56 } else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
60 } else if ((IS_ENABLED(STM32_PLL_SRC_CSI) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
80 return get_pllsrc_frequency(PLL1_ID); in get_startup_frequency()
101 return get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in get_sysclk_frequency()
283 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
289 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
295 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
464 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()
Dclock_stm32_ll_u5.c35 #define PLL1_ID 1 macro
57 if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
61 } else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
65 } else if ((IS_ENABLED(STM32_PLL_SRC_MSIS) && pll_id == PLL1_ID) || in get_pllsrc_frequency()
85 return get_pllsrc_frequency(PLL1_ID); in get_startup_frequency()
106 return get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in get_sysclk_frequency()
298 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
304 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
310 *rate = get_pllout_frequency(get_pllsrc_frequency(PLL1_ID), in stm32_clock_control_get_subsys_rate()
552 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range, PLL1_ID); in set_up_plls()