Searched refs:P19 (Results 1 – 16 of 16) sorted by relevance
24 * - Connect LPADC0 CH0A signal to voltage between 0~3.3V (P19 pin 4)25 * - Connect LPADC0 CH0B signal to voltage between 0~3.3V (P19 pin 2)34 * CH0A (plus side) is routed to P19 pin 435 * CH0B (minus side) is routed to P19 pin 2
93 #define P19 CYHAL_PORT_19 macro
21 * CH0A is routed to P19 pin 4
50 ground and the white wire to the SCL pin, i.e. pin P19 on the edge connector.
99 <19 0 &gpio0 26 0>, /* P19 */
83 <19 0 &gpio0 12 0>; /* P19, P0.12/TRACECLK */
77 <19 0 &gpio0 12 0>; /* P19, P0.12/TRACECLK */
97 - SPI0_TX : P19
101 <19 0 &gpio0 0 0>, /* P19, I2C1 SCL */
107 - SPI0_TX : P19
125 | P19 | GPIO_B1_15 | D19 | GPIO2_IO31 | | |
105 (P16-P19), with the reset and interrupt signal for the W5500 routed to P20 and126 - SPI0_TX : P19
105 | P19 | GPIO_AD_B1_10 | D19 | GPIO1_IO26 | | |
128 - SPI0_TX : P19
