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/Zephyr-latest/drivers/clock_control/
Dclock_control_litex.h58 #define CLKOUT_INIT(N) \ argument
59 BUILD_ASSERT(CLKOUT_DUTY_DEN(N) > 0 && \
60 CLKOUT_DUTY_NUM(N) > 0 && \
61 CLKOUT_DUTY_NUM(N) <= CLKOUT_DUTY_DEN(N), \
63 BUILD_ASSERT(CLKOUT_ID(N) < NCLKOUT, "Invalid CLKOUT index"); \
64 lcko = &ldev->clkouts[N]; \
65 lcko->id = CLKOUT_ID(N); \
68 lcko->def.freq = CLKOUT_FREQ(N); \
69 lcko->def.phase = CLKOUT_PHASE(N); \
70 lcko->def.duty.num = CLKOUT_DUTY_NUM(N); \
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_mtk_adsp.c61 #define DEV_INIT(N) \ argument
62 IRQ_CONNECT(DT_INST_IRQN(N), 0, intc_isr, DEVICE_DT_INST_GET(N), 0); \
63 dev_init(DEVICE_DT_INST_GET(N));
73 #define DEF_DEV(N) \ argument
74 static const struct intc_mtk_cfg dev_cfg##N = { \
75 .xtensa_irq = DT_INST_IRQN(N), \
76 .irq_mask = DT_INST_PROP(N, mask), \
77 .sw_isr_off = (N + 1) * 32, \
78 .enable_reg = (void *)DT_INST_REG_ADDR(N), \
79 .status_reg = (void *)DT_INST_PROP(N, status_reg) }; \
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/Zephyr-latest/soc/mediatek/mt8xxx/
Dmbox.c104 #define DEF_IRQ(N) \ argument
105 { IRQ_CONNECT(DT_INST_IRQN(N), 0, mbox_isr, DEVICE_DT_INST_GET(N), 0); \
106 irq_enable(DT_INST_IRQN(N)); }
117 #define DEF_DEV(N) \ argument
118 static struct mbox_data dev_data##N; \
119 static const struct mbox_cfg dev_cfg##N = \
120 { .irq = DT_INST_IRQN(N), .mbox = (void *)DT_INST_REG_ADDR(N), }; \
121 DEVICE_DT_INST_DEFINE(N, NULL, NULL, &dev_data##N, &dev_cfg##N, \
/Zephyr-latest/tests/benchmarks/app_kernel/
DREADME.txt18 | S I M P L E S E R V I C E M E A S U R E M E N T S | nsec |
39 | M A I L B O X M E A S U R E M E N T S |
46 | N| NNNNNN| N|
47 | N| NNNNNN| NN|
62 | P I P E M E A S U R E M E N T S |
72 | N| N| NNNNNNN| NNNNNNN| NNNNNNN| N| N| N|
89 | N| NNNN| NNNNNNN| NNNNNNN| NNNNNNN| N| N| N|
98 | NNNN| N| NNNNNNNNN| NNNNNNNNN| NNNNNNNNN| N| N| N|
106 | N| NNNN| NNNNNNN| NNNNNN| NNNNNN| N| N| N|
114 | NNNN| NN| NNNNNNNNN| NNNNNNNNN| NNNNNNN| NN| N| NNN|
[all …]
/Zephyr-latest/doc/hardware/arch/
Darc-support-status.rst21 **Y** - yes, supported; **N** - no, not supported; **WIP** - Work In Progress;
42 …r fast interrupts | Y | Y | TBD | N | N |
46 | Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | …
48 … | Y | Y | Y | N | N |
50 | Hardware-assisted atomic operations | N/A | Y | …
52 | DSP ISA | Y | N [#f3]_ | …
54 …ensions | Y | N [#f3]_ | N/A …
56 … | Y | Y | N | TB…
58 … | Y | Y | TBD | N | N |
60 …MMU) | N/A | N | TBD | N …
[all …]
Darm_cortex_m.rst30 … | Y | N | Y | Y | Y | N …
44 | | Zero Latency interrupts | N | N |…
48 | Native system timer (SysTick) | | N [#f1]_ | Y |…
52 | | User mode | N | Y |…
54 | | HW stack protection (MPU) | N | N |…
56 … | HW-assisted stack limit checking | N | N | N | N | …
59 | dereference detection | | N | N |…
61 …s | | N | N | Y | Y | Y …
63 …ions| | N | N | Y | Y | Y …
65 … | | N | N | Y | Y | Y …
[all …]
/Zephyr-latest/boards/intel/adl/doc/
Dindex.rst3 Alder Lake N
11 Currently supported is N-processor line, Single Chip Platform that consists of
12 the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on
15 Proposed branding for Adler Lake N is Intel Processor (N100,N200) and
18 Alder Lake N Customer Reference Board (ADL-N CRB) and Alder Lake Reference
19 Validation Platform (ADL-N RVP) are example implementations of compact single
22 This board configuration enables kernel support for the Alder Lake N boards.
36 Use the following procedures for booting an image for an Alder Lake N CRB board.
47 application for Alder Lake N CRB:
59 Booting the Alder Lake N CRB Board using UEFI
/Zephyr-latest/boards/beagle/beagleplay/doc/
Dbeagleplay_cc1352p7.rst84 | DIO5 | N/C | |
86 | DIO6 | N/C | |
88 | DIO7 | N/C | |
90 | DIO8 | N/C | |
92 | DIO9 | N/C | |
94 | DIO10 | N/C | |
96 | DIO11 | N/C | |
102 | DIO14 | N/C | |
110 | DIO18 | N/C | |
112 | DIO19 | N/C | |
[all …]
/Zephyr-latest/tests/posix/shm/src/
Dmain.c32 #define N (CONFIG_ZVFS_OPEN_MAX - 3) macro
35 BUILD_ASSERT(N >= 2, "CONFIG_ZVFS_OPEN_MAX must be > 4");
42 int fd[N]; in ZTEST()
76 for (size_t i = 0; i < N; ++i) { in ZTEST()
82 for (size_t i = N; i > 0; --i) { in ZTEST()
112 int fd[N]; in ZTEST()
114 for (size_t i = 0; i < N; ++i) { in ZTEST()
144 for (size_t i = N; i > 0; --i) { in ZTEST()
153 int fd[N]; in ZTEST()
154 void *addr[N]; in ZTEST()
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/Zephyr-latest/samples/subsys/rtio/sensor_batch_processing/src/
Dmain.c13 #define N (8) macro
14 #define M (N/2)
15 #define SQ_SZ (N)
16 #define CQ_SZ (N)
23 RTIO_DEFINE_WITH_MEMPOOL(ez_io, SQ_SZ, CQ_SZ, N, SAMPLE_SIZE, 4);
31 for (int n = 0; n < N; n++) { in main()
/Zephyr-latest/kernel/include/
Dgen_offset.h90 #define GEN_NAMED_OFFSET_SYM(S, M, N) \ argument
91 GEN_ABSOLUTE_SYM(__##S##_##N##_##OFFSET, offsetof(S, M))
93 #define GEN_NAMED_OFFSET_STRUCT(S, M, N) \ argument
94 GEN_ABSOLUTE_SYM(__struct_##S##_##N##_##OFFSET, offsetof(struct S, M))
/Zephyr-latest/drivers/misc/devmux/
Ddevmux.c27 #define N DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) macro
29 static const struct device *devmux_devices[N];
30 static const struct devmux_config *devmux_configs[N];
31 static struct devmux_data *devmux_datas[N];
35 for (size_t i = 0; i < N; ++i) { in devmux_device_is_valid()
46 for (size_t i = 0; i < N; i++) { in devmux_inst_get()
57 for (size_t i = 0; i < N; i++) { in devmux_config_get()
68 for (size_t i = 0; i < N; i++) { in devmux_data_get()
/Zephyr-latest/tests/kconfig/configdefault/
DKconfig20 bool "SYM N 1"
36 bool "SYM N 2"
51 bool "SYM N 3"
68 bool "SYM N 4"
79 bool "SYM N 5"
96 bool "SYM N 6"
112 bool "SYM N 7"
125 bool "SYM N 8"
142 bool "SYM N 9" if DEP_Y
156 bool "SYM N 10" if DEP_N
[all …]
/Zephyr-latest/boards/u-blox/ubx_bmd345eval/doc/
Dindex.rst198 | 7 | N/C |
200 | 8 | N/C |
224 | 7 | N/C |
226 | 8 | N/C |
305 | 1 | VSHLD | N/A |
307 | 2 | VSHLD | N/A |
311 | 4 | VSHLD | N/A |
313 | 5 | V5V | N/A |
315 | 6 | GND | N/A |
317 | 7 | GND | N/A |
[all …]
/Zephyr-latest/tests/kernel/threads/dynamic_thread_stack/src/
Dmain.c128 size_t N; in ZTEST() local
142 for (N = 0; N < MAX_HEAP_STACKS; ++N) { in ZTEST()
143 stack[N] = k_thread_stack_alloc(CONFIG_DYNAMIC_THREAD_STACK_SIZE, in ZTEST()
145 if (stack[N] == NULL) { in ZTEST()
151 for (size_t i = 0; i < N; ++i) { in ZTEST()
160 for (size_t i = 0; i < N; ++i) { in ZTEST()
166 for (size_t i = 0; i < N; ++i) { in ZTEST()
/Zephyr-latest/include/zephyr/sys/
Dutil_macro.h383 #define GET_ARG_N(N, ...) Z_GET_ARG_##N(__VA_ARGS__) argument
393 #define GET_ARGS_LESS_N(N, ...) Z_GET_ARGS_LESS_##N(__VA_ARGS__) argument
714 #define MACRO_MAP_CAT_N(N, ...) MACRO_MAP_CAT_N_(N, __VA_ARGS__) argument
/Zephyr-latest/drivers/timer/
DKconfig.riscv_machine30 A clock obtained by dividing the system clock by a value of [2^N] is
31 supplied to the timer. Where N is this parameter's value.
32 When N=2, it is divided by 4, and when N=5, it is divided by 32.
33 Default case is N=0, this means use system clock as machine timer clock.
/Zephyr-latest/tests/lib/hash_map/src/
Dclear.c14 const size_t N = 10; in ZTEST() local
17 for (size_t i = 0; i < N; ++i) { in ZTEST()
21 zassert_equal(N, sys_hashmap_size(&map)); in ZTEST()
/Zephyr-latest/tests/drivers/console_switching/src/
Dmain.c37 for (size_t i = 0, j = 0, N = ARRAY_SIZE(devs); i < 2 * N; i++, j++, j %= N) { in ZTEST() local
71 for (size_t i = 0, j = 0, N = ARRAY_SIZE(devs); i < 2 * N; i++, j++, j %= N) { in ZTEST() local
/Zephyr-latest/tests/unit/intmath/
Dmain.c24 #define NEG_CHECK(T, N) BUILD_ASSERT((-((T)N)) == (~((T)N)) + 1) argument
/Zephyr-latest/boards/u-blox/ubx_bmd360eval/doc/
Dindex.rst181 | 7 | N/C |
183 | 8 | N/C |
227 | 1 | VSHLD | N/A |
229 | 2 | VSHLD | N/A |
233 | 4 | VSHLD | N/A |
235 | 5 | V5V | N/A |
237 | 6 | GND | N/A |
239 | 7 | GND | N/A |
241 | 8 | N/C | N/A |
295 | 4 | GND | N/A |
[all …]
/Zephyr-latest/boards/nordic/nrf52dk/doc/
Dindex.rst143 | 1 | VDD | N/A |
147 | 3 | GND | N/A |
151 | 5 | GND | N/A |
156 | 7 | Cut off | N/A |
158 | 8 | Cut off | N/A |
160 | 9 | GND | N/A |
246 | 1 | VDD | N/A |
248 | 2 | VDD | N/A |
252 | 4 | VDD | N/A |
254 | 5 | V5V | N/A |
[all …]
/Zephyr-latest/boards/u-blox/ubx_bmd330eval/doc/
Dindex.rst183 | 7 | N/C |
185 | 8 | N/C |
229 | 1 | VSHLD | N/A |
231 | 2 | VSHLD | N/A |
235 | 4 | VSHLD | N/A |
237 | 5 | V5V | N/A |
239 | 6 | GND | N/A |
241 | 7 | GND | N/A |
243 | 8 | N/C | N/A |
297 | 4 | GND | N/A |
[all …]
/Zephyr-latest/boards/snps/emsdp/doc/
Dindex.rst30 | Caches | N | Y | N | Y | Y | N | Y |
32 | DSP | N | N | Y | Y | Y | Y | Y |
34 | XY Memory | N | N | N | N | N | Y | Y |
36 | Secure | N | N | N | N | Y | N | N |
44 | SDIO | on-chip | N | SD-card controller |
52 | ADC | 1 Pmod | N | adc (via spi) |
54 | I2C | Arduino + | N | i2c |
60 | PWM | Arduino + | N | pwm |
63 | I2S | on-chip | N | Audio interface |
/Zephyr-latest/boards/u-blox/ubx_bmd300eval/doc/
Dindex.rst187 | 7 | N/C |
189 | 8 | N/C |
233 | 1 | VSHLD | N/A |
235 | 2 | VSHLD | N/A |
239 | 4 | VSHLD | N/A |
241 | 5 | V5V | N/A |
243 | 6 | GND | N/A |
245 | 7 | GND | N/A |
247 | 8 | N/C | N/A |
304 | 4 | GND | N/A |
[all …]

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