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Searched refs:MSR (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_uart.h172 volatile uint8_t MSR; member
/Zephyr-latest/drivers/can/
Dcan_stm32_bxcan.c295 if (can->MSR & CAN_MSR_ERRI) { in can_stm32_isr()
297 can->MSR |= CAN_MSR_ERRI; in can_stm32_isr()
319 if (can->MSR & CAN_MSR_ERRI) { in can_stm32_state_change_isr()
322 can->MSR |= CAN_MSR_ERRI; in can_stm32_state_change_isr()
335 while ((can->MSR & CAN_MSR_INAK) == 0U) { in can_stm32_enter_init_mode()
352 while ((can->MSR & CAN_MSR_INAK) != 0U) { in can_stm32_leave_init_mode()
368 while ((can->MSR & CAN_MSR_SLAK) != 0) { in can_stm32_leave_sleep_mode()
/Zephyr-latest/drivers/i2c/
Di2c_mcux_lpi2c_rtio.c233 if (0 != (base->MSR & LPI2C_MSR_NDF_MASK)) { in mcux_lpi2c_complete()
Di2c_mcux_lpi2c.c218 if (0 != (base->MSR & LPI2C_MSR_NDF_MASK)) { in mcux_lpi2c_transfer()
/Zephyr-latest/drivers/serial/
Duart_ns16550.c257 #define MSR(dev) (get_port(dev) + (REG_MSR * reg_interval(dev))) macro
/Zephyr-latest/doc/hardware/arch/
Darm_cortex_m.rst185 * has a relatively low runtime overhead (programming is done with MSR instructions)