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Searched refs:MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/soc/nxp/imx/imx8m/m7/
Dpinctrl_soc.h21 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
32 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx9/imx93/
Dpinctrl_soc.h19 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT macro
29 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx8m/a53/
Dpinctrl_soc.h21 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
32 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/
Dpinctrl_soc.h21 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
32 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/
Dpinctrl_soc.h21 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
32 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx8m/m4_quad/
Dpinctrl_soc.h21 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
31 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imx/imx6sx/
Dpinctrl_soc.h26 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT 11 macro
42 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/soc/nxp/imxrt/imxrt10xx/
Dpinctrl_soc.h23 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT macro
39 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) | \
/Zephyr-latest/drivers/gpio/
Dgpio_mcux_igpio.c166 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_igpio_configure()
168 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_igpio_configure()
180 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_igpio_configure()
182 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_igpio_configure()
Dgpio_imx.c53 #ifdef MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT in imx_gpio_configure()
56 reg |= BIT(MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in imx_gpio_configure()
58 reg &= ~BIT(MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in imx_gpio_configure()
Dgpio_mcux_rgpio.c112 reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_rgpio_configure()
114 reg &= ~(0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); in mcux_rgpio_configure()