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Searched refs:MCPWM0_INTR_SOURCE (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Desp-esp32c6-intmux.h71 #define MCPWM0_INTR_SOURCE 61 /* interrupt of MCPWM0, LEVEL*/ macro
/Zephyr-latest/dts/riscv/espressif/esp32c6/
Desp32c6_common.dtsi270 interrupts = <MCPWM0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;