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Searched refs:LSR (Results 1 – 6 of 6) sorted by relevance

/Zephyr-latest/soc/microchip/mec/mec15xx/
Ddevice_power.c154 while ((UART0_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) { in deep_sleep_save_uarts()
160 while ((UART1_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) { in deep_sleep_save_uarts()
166 while ((UART2_REGS->LSR & MCHP_UART_LSR_TEMT) == 0) { in deep_sleep_save_uarts()
/Zephyr-latest/arch/arm/include/cortex_m/
Ddwt.h52 uint32_t lsr = DWT->LSR; in dwt_access()
/Zephyr-latest/drivers/serial/
Duart_mchp_xec.c566 if ((regs->LSR & LSR_RXRDY) != 0) { in uart_xec_poll_in()
596 while ((regs->LSR & LSR_THRE) == 0) { in uart_xec_poll_out()
619 int check = regs->LSR & LSR_EOB_MASK; in uart_xec_err_check()
646 for (i = 0; (i < size) && (regs->LSR & LSR_THRE) != 0; i++) { in uart_xec_fifo_fill()
676 for (i = 0; (i < size) && (regs->LSR & LSR_RXRDY) != 0; i++) { in uart_xec_fifo_read()
754 ((regs->LSR & (LSR_TEMT | LSR_THRE)) != (LSR_TEMT | LSR_THRE))) { in uart_xec_irq_tx_complete()
928 rx_ready = ((regs->LSR & LSR_RXRDY) == LSR_RXRDY) ? 1 : 0; in uart_xec_isr()
Duart_ns16550.c256 #define LSR(dev) (get_port(dev) + (REG_LSR * reg_interval(dev))) macro
535 if ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_RXRDY) != 0) {
931 while ((ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_THRE) == 0) {
952 int check = (ns16550_inbyte(dev_cfg, LSR(dev)) & LSR_EOB_MASK);
1117 int ret = ((ns16550_inbyte(dev_cfg, LSR(dev)) & (LSR_TEMT | LSR_THRE))
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_uart.h171 volatile uint8_t LSR; member
/Zephyr-latest/soc/microchip/mec/mec172x/
Ddevice_power.c174 while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) { in deep_sleep_save_uarts()
182 while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) { in deep_sleep_save_uarts()