Searched refs:LPUART1_SEL (Results 1 – 15 of 15) sorted by relevance
| /Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/boards/ |
| D | nucleo_wl55jc.overlay | 11 <&rcc STM32_SRC_LSE LPUART1_SEL(3)>;
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| D | stm32l562e_dk.overlay | 24 <&rcc STM32_SRC_LSE LPUART1_SEL(3)>;
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| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32wb0_clock.h | 65 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG) /* WB05/WB09 only */ macro
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| D | stm32l0_clock.h | 72 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32wb_clock.h | 81 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32wl_clock.h | 80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32u0_clock.h | 79 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32wba_clock.h | 96 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG) macro
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| D | stm32g0_clock.h | 80 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32g4_clock.h | 84 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32l4_clock.h | 85 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG) macro
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| D | stm32h7rs_clock.h | 126 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG) macro
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| D | stm32h7_clock.h | 128 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG) macro
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| D | stm32u5_clock.h | 127 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG) macro
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| D | stm32h5_clock.h | 126 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR3_REG) macro
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