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Searched refs:GENMASK (Results 1 – 25 of 229) sorted by relevance

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/Zephyr-latest/include/zephyr/drivers/mfd/
Dmax22017.h18 #define MAX22017_GEN_ID_PROD_ID GENMASK(15, 8)
19 #define MAX22017_GEN_ID_REV_ID GENMASK(7, 0)
22 #define MAX22017_GEN_SERIAL_MSB_SERIAL_MSB GENMASK(15, 0)
25 #define MAX22017_GEN_SERIAL_LSB_SERIAL_LSB GENMASK(15, 0)
28 #define MAX22017_GEN_CNFG_OPENWIRE_DTCT_CNFG GENMASK(15, 14)
29 #define MAX22017_GEN_CNFG_TMOUT_SEL GENMASK(13, 10)
32 #define MAX22017_GEN_CNFG_THSHDN_CNFG GENMASK(7, 6)
33 #define MAX22017_GEN_CNFG_OVC_SHDN_CNFG GENMASK(5, 4)
34 #define MAX22017_GEN_CNFG_OVC_CNFG GENMASK(3, 2)
39 #define MAX22017_GEN_GPIO_CTRL_GPIO_EN GENMASK(13, 8)
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/Zephyr-latest/soc/intel/intel_adsp/ace/
Dcomm_widget.h33 #define DSATTR_DSTPID GENMASK(7, 0)
41 #define DSATTR_SRCPID GENMASK(15, 8)
49 #define DSATTR_OPC GENMASK(23, 16)
57 #define DSATTR_BE GENMASK(27, 24)
63 #define DSATTR_RSVD31 GENMASK(31, 28)
90 #define DSUADDR_UADDR GENMASK(15, 0)
96 #define DSUADDR_RSVD30 GENMASK(30, 16)
121 #define DSSAI_SAI GENMASK(15, 0)
129 #define DSSAI_RS GENMASK(19, 16)
135 #define DSSAI_RSVD30 GENMASK(30, 20)
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Dpmc_interface.h20 #define CW_PMC_IPC_OP_CODE GENMASK(7, 0)
26 #define CW_PMC_IPC_CC GENMASK(7, 0)
31 #define CW_PMC_IPC_PARAM1 GENMASK(15, 8)
36 #define CW_PMC_IPC_PARAM2 GENMASK(23, 16)
41 #define CW_PMC_IPC_PARAM3 GENMASK(27, 24)
46 #define CW_PMC_IPC_RSVD GENMASK(30, 28)
80 #define CW_PMC_IPC_SRAM_USED_BANKS GENMASK(17, 8)
85 #define CW_PMC_IPC_SRAM_RESERVED GENMASK(30, 18)
/Zephyr-latest/soc/intel/intel_adsp/ace/include/
Ddmic_regs.h40 #define TS_LOCAL_TSCTRL_DMATS GENMASK(13, 12)
43 #define TS_LOCAL_TSCTRL_CLNKS GENMASK(11, 10)
55 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0)
58 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12)
61 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0)
167 #define OUTCONTROL_BFTH GENMASK(23, 20)
170 #define OUTCONTROL_OF GENMASK(19, 18)
174 #define OUTCONTROL_IPM GENMASK(17, 15)
177 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13)
180 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11)
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/Zephyr-latest/soc/intel/intel_adsp/cavs/include/cavs25/
Ddmic_regs.h52 #define TS_LOCAL_TSCTRL_CDMAS GENMASK(4, 0)
55 #define TS_LOCAL_OFFS_FRM GENMASK(15, 12)
58 #define TS_LOCAL_OFFS_CLK GENMASK(11, 0)
164 #define OUTCONTROL_BFTH GENMASK(23, 20)
167 #define OUTCONTROL_OF GENMASK(19, 18)
171 #define OUTCONTROL_IPM GENMASK(17, 16)
174 #define OUTCONTROL_IPM_SOURCE_1 GENMASK(14, 13)
177 #define OUTCONTROL_IPM_SOURCE_2 GENMASK(12, 11)
180 #define OUTCONTROL_IPM_SOURCE_3 GENMASK(10, 9)
183 #define OUTCONTROL_IPM_SOURCE_4 GENMASK(8, 7)
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/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Ddmic_regs_ace1x.h17 #define DMICLCAP_LCOUNT GENMASK(2, 0)
38 #define DMICLCAP_PGD GENMASK(30, 28)
45 #define DMICIPPTR_PTR GENMASK(20, 0)
48 #define DMICIPPTR_VER GENMASK(23, 21)
55 #define DMICSYNC_SYNCPRD GENMASK(14, 0)
74 #define DMICPCMSCAP_ISS GENMASK(3, 0)
77 #define DMICPCMSCAP_OSS GENMASK(7, 4)
80 #define DMICPCMSCAP_BSS GENMASK(12, 8)
91 #define DMICPCMSyCM_LCHAN GENMASK(3, 0)
94 #define DMICPCMSyCM_HCHAN GENMASK(7, 4)
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/Zephyr-latest/drivers/ethernet/
Deth_smsc91x_priv.h13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
15 #define BSR_IDENTIFY_MASK GENMASK(15, 8)
35 #define ECR_SNGLCOL_MASK GENMASK(3, 0) /* Single collisions */
36 #define ECR_MULCOL_MASK GENMASK(7, 4) /* Multiple collisions */
37 #define ECR_TX_DEFR_MASK GENMASK(11, 8) /* Transmit deferrals */
38 #define ECR_EXC_DEFR_MASK GENMASK(15, 12) /* Excessive deferrals */
42 #define MIR_SIZE_MASK GENMASK(7, 0) /* Memory size (2k pages) */
43 #define MIR_FREE_MASK GENMASK(15, 8) /* Memory free (2k pages) */
50 #define RPCR_LSA_MASK GENMASK(7, 5)
51 #define RPCR_LSB_MASK GENMASK(4, 2)
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Deth_dwmac_priv.h98 #define MAC_CONF_SARC GENMASK(30, 28)
100 #define MAC_CONF_IPG GENMASK(26, 24)
117 #define MAC_CONF_BL GENMASK(6, 5)
119 #define MAC_CONF_PRELEN GENMASK(3, 2)
128 #define MAC_EXT_CONF_EIPG GENMASK(29, 25)
130 #define MAC_EXT_CONF_HDSMS GENMASK(22, 20)
135 #define MAC_EXT_CONF_GPSL GENMASK(13, 0)
148 #define MAC_PKT_FILTER_PCF GENMASK(7, 6)
161 #define MAC_WDOG_TIMEOUT_WTO GENMASK(3, 0)
176 #define MAC_VLAN_TAG_CTRL_EIVLS GENMASK(29, 28)
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Doa_tc6.h16 #define MMS_REG(m, r) ((((m) & GENMASK(3, 0)) << 16) | ((r) & GENMASK(15, 0)))
30 #define OA_BUFSTS_TXC GENMASK(15, 8)
31 #define OA_BUFSTS_RCA GENMASK(7, 0)
47 #define OA_CTRL_HDR_MMS GENMASK(27, 24)
48 #define OA_CTRL_HDR_ADDR GENMASK(23, 8)
49 #define OA_CTRL_HDR_LEN GENMASK(7, 1)
58 #define OA_DATA_HDR_SWO GENMASK(19, 16)
60 #define OA_DATA_HDR_EBO GENMASK(13, 8)
67 #define OA_DATA_FTR_RCA GENMASK(28, 24)
70 #define OA_DATA_FTR_SWO GENMASK(19, 16)
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/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h88 #define MCP251XFD_REG_CON_TXBWS_MASK GENMASK(31, 28)
90 #define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
99 #define MCP251XFD_REG_CON_OPMOD_MASK GENMASK(23, 21)
107 #define MCP251XFD_REG_CON_WFT_MASK GENMASK(10, 9)
115 #define MCP251XFD_REG_CON_DNCNT_MASK GENMASK(4, 0)
121 #define MCP251XFD_REG_NBTCFG_BRP_MASK GENMASK(31, 24)
122 #define MCP251XFD_REG_NBTCFG_TSEG1_MASK GENMASK(23, 16)
123 #define MCP251XFD_REG_NBTCFG_TSEG2_MASK GENMASK(14, 8)
124 #define MCP251XFD_REG_NBTCFG_SJW_MASK GENMASK(6, 0)
127 #define MCP251XFD_REG_DBTCFG_BRP_MASK GENMASK(31, 24)
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/Zephyr-latest/drivers/charger/
Dbq24190.h14 #define BQ24190_REG_ISC_VINDPM_MASK GENMASK(6, 3)
16 #define BQ24190_REG_ISC_IINLIM_MASK GENMASK(2, 0)
25 #define BQ24190_REG_POC_CHG_CONFIG_MASK GENMASK(5, 4)
31 #define BQ24190_REG_POC_SYS_MIN_MASK GENMASK(3, 1)
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK GENMASK(7, 4)
57 #define BQ24190_REG_PCTCC_ITERM_MASK GENMASK(3, 0)
66 #define BQ24190_REG_CVC_VREG_MASK GENMASK(7, 2)
83 #define BQ24190_REG_CTTC_WATCHDOG_MASK GENMASK(5, 4)
87 #define BQ24190_REG_CTTC_CHG_TIMER_MASK GENMASK(2, 1)
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/Zephyr-latest/soc/neorv32/
Dsoc.h17 #define NEORV32_SYSINFO_MISC_IMEM GENMASK(7, 0)
18 #define NEORV32_SYSINFO_MISC_DMEM GENMASK(15, 8)
19 #define NEORV32_SYSINFO_MISC_HART GENMASK(23, 16)
20 #define NEORV32_SYSINFO_MISC_BOOT GENMASK(31, 24)
53 #define NEORV32_SYSINFO_CACHE_INST_BLOCK_SIZE GENMASK(3, 0)
54 #define NEORV32_SYSINFO_CACHE_INST_NUM_BLOCKS GENMASK(7, 4)
55 #define NEORV32_SYSINFO_CACHE_DATA_BLOCK_SIZE GENMASK(11, 8)
56 #define NEORV32_SYSINFO_CACHE_DATA_NUM_BLOCKS GENMASK(15, 12)
57 #define NEORV32_SYSINFO_CACHE_XBUS_BLOCK_SIZE GENMASK(27, 24)
58 #define NEORV32_SYSINFO_CACHE_XBUS_NUM_BLOCKS GENMASK(31, 28)
/Zephyr-latest/include/zephyr/drivers/can/
Dcan_mcan.h26 #define CAN_MCAN_CREL_REL GENMASK(31, 28)
27 #define CAN_MCAN_CREL_STEP GENMASK(27, 24)
28 #define CAN_MCAN_CREL_SUBSTEP GENMASK(23, 20)
29 #define CAN_MCAN_CREL_YEAR GENMASK(19, 16)
30 #define CAN_MCAN_CREL_MON GENMASK(15, 8)
31 #define CAN_MCAN_CREL_DAY GENMASK(7, 0)
35 #define CAN_MCAN_ENDN_ETV GENMASK(31, 0)
39 #define CAN_MCAN_CUST_CUST GENMASK(31, 0)
44 #define CAN_MCAN_DBTP_DBRP GENMASK(20, 16)
45 #define CAN_MCAN_DBTP_DTSEG1 GENMASK(12, 8)
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/Zephyr-latest/drivers/mspi/
Dmspi_dw.h13 #define CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
18 #define CTRLR0_TMOD_MASK GENMASK(11, 10)
25 #define CTRLR0_FRF_MASK GENMASK(7, 6)
29 #define CTRLR0_DFS_MASK GENMASK(4, 0)
32 #define CTRLR1_NDF_MASK GENMASK(15, 0)
38 #define TXFTLR_TXFTHR_MASK GENMASK(23, 16)
39 #define TXFTLR_TFT_MASK GENMASK(7, 0)
42 #define RXFTLR_RFT_MASK GENMASK(7, 0)
45 #define TXFLR_TXTFL_MASK GENMASK(7, 0)
48 #define RXFLR_RXTFL_MASK GENMASK(7, 0)
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/Zephyr-latest/subsys/bluetooth/host/classic/
Davrcp_internal.h53 #define BT_AVRCP_HDR_GET_CTYPE_OR_RSP(hdr) FIELD_GET(GENMASK(3, 0), ((hdr)->byte0))
59 #define BT_AVRCP_HDR_GET_SUBUNIT_ID(hdr) FIELD_GET(GENMASK(2, 0), ((hdr)->byte1))
65 #define BT_AVRCP_HDR_GET_SUBUNIT_TYPE(hdr) FIELD_GET(GENMASK(7, 3), ((hdr)->byte1))
69 (hdr)->byte0 = (((hdr)->byte0) & ~GENMASK(3, 0)) | FIELD_PREP(GENMASK(3, 0), (ctype))
76 (hdr)->byte1 = (((hdr)->byte1) & ~GENMASK(2, 0)) | FIELD_PREP(GENMASK(2, 0), (subunit_id))
83 (hdr)->byte1 = (((hdr)->byte1) & ~GENMASK(7, 3)) | FIELD_PREP(GENMASK(7, 3), (subunit_type))
/Zephyr-latest/include/zephyr/usb_c/
Dtcpci.h31 #define TCPC_REG_TC_REV_MAJOR_MASK GENMASK(7, 4)
35 #define TCPC_REG_TC_REV_MINOR_MASK GENMASK(3, 0)
42 #define TCPC_REG_PD_REV_REV_MAJOR_MASK GENMASK(15, 12)
46 #define TCPC_REG_PD_REV_REV_MINOR_MASK GENMASK(11, 8)
50 #define TCPC_REG_PD_REV_VER_MAJOR_MASK GENMASK(7, 4)
54 #define TCPC_REG_PD_REV_VER_MINOR_MASK GENMASK(3, 0)
61 #define TCPC_REG_PD_INT_REV_REV_MAJOR_MASK GENMASK(15, 12)
65 #define TCPC_REG_PD_INT_REV_REV_MINOR_MASK GENMASK(11, 8)
69 #define TCPC_REG_PD_INT_REV_VER_MAJOR_MASK GENMASK(7, 4)
73 #define TCPC_REG_PD_INT_REV_VER_MINOR_MASK GENMASK(3, 0)
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/Zephyr-latest/drivers/spi/
Dspi_andes_atcspi200.h49 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
50 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
57 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
58 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
76 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
77 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
80 #define STAT_RX_NUM_MSK GENMASK(12, 8)
81 #define STAT_TX_NUM_MSK GENMASK(20, 16)
93 #define CTRL_RX_THRES_MSK GENMASK(12, 8)
94 #define CTRL_TX_THRES_MSK GENMASK(20, 16)
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/Zephyr-latest/drivers/sensor/vishay/vcnl36825t/
Dvcnl36825t.h41 #define VCNL36825T_PS_ON_MSK GENMASK(1, 1)
59 #define VCNL36825T_PS_ST_MSK GENMASK(0, 0)
60 #define VCNL36825T_PS_SMART_PERS_MSK GENMASK(1, 1)
61 #define VCNL36825T_PS_INT_MSK GENMASK(3, 2)
62 #define VCNL36825T_PS_PERS_MSK GENMASK(5, 4)
110 #define VCNL36825T_PS_TRIG_MSK GENMASK(5, 5)
111 #define VCNL36825T_PS_AF_MSK GENMASK(6, 6)
147 #define VCNL36825T_PS_LPEN_MSK GENMASK(8, 8)
180 #define VCNL36825T_PS_DATA_L_MSK GENMASK(7, 0)
181 #define VCNL36825T_PS_DATA_H_MSK GENMASK(11, 8)
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/Zephyr-latest/include/zephyr/drivers/rtc/
Drtc_ds3231.h44 #define DS3231_BITS_TIME_SECONDS GENMASK(6, 0)
45 #define DS3231_BITS_TIME_MINUTES GENMASK(6, 0)
46 #define DS3231_BITS_TIME_HOURS GENMASK(5, 0)
49 #define DS3231_BITS_TIME_DAY_OF_WEEK GENMASK(2, 0)
50 #define DS3231_BITS_TIME_DATE GENMASK(5, 0)
51 #define DS3231_BITS_TIME_MONTH GENMASK(4, 0)
53 #define DS3231_BITS_TIME_YEAR GENMASK(7, 0)
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h21 #define GET_PAGE_SIZE(x) (FIELD_GET(GENMASK(15, 0), x))
22 #define GET_PAGES_PER_BLOCK(x) (FIELD_GET(GENMASK(15, 0), x))
23 #define GET_SPARE_SIZE(x) (FIELD_GET(GENMASK(31, 16), x))
24 #define ONFI_TIMING_MODE_SDR(x) (FIELD_GET(GENMASK(15, 0), x))
25 #define ONFI_TIMING_MODE_NVDDR(x) (FIELD_GET(GENMASK(31, 15), x))
28 #define CNF_GET_NLUNS(x) (FIELD_GET(GENMASK(7, 0), x))
29 #define CNF_GET_DEV_TYPE(x) (FIELD_GET(GENMASK(31, 30), x))
98 #define CNF_OPR_WORK_MODE_SDR_MASK (GENMASK(1, 0))
127 #define CNF_ASYNC_TIMINGS_TRH FIELD_PREP(GENMASK(28, 24), 2)
128 #define CNF_ASYNC_TIMINGS_TRP FIELD_PREP(GENMASK(20, 16), 4)
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Dflash_andes_qspi.h48 #define TFMAT_DATA_LEN_MSK GENMASK(12, 8)
57 #define TCTRL_TRNS_MODE_MSK GENMASK(27, 24)
87 #define CFG_RX_FIFO_SIZE_MSK GENMASK(3, 0)
88 #define CFG_TX_FIFO_SIZE_MSK GENMASK(7, 4)
91 #define STAT_RX_NUM_MSK GENMASK(13, 8)
92 #define STAT_TX_NUM_MSK GENMASK(21, 16)
98 #define CTRL_RX_THRES_MSK GENMASK(15, 8)
99 #define CTRL_TX_THRES_MSK GENMASK(23, 16)
102 #define TIMIN_SCLK_DIV_MSK GENMASK(7, 0)
/Zephyr-latest/drivers/sensor/ti/tmag5273/
Dtmag5273.h52 #define TMAG5273_CONV_AVB_MSK GENMASK(4, 2)
79 #define TMAG5273_OPERATING_MODE_MSK GENMASK(1, 0)
129 #define TMAG5273_ANGLE_EN_MSK GENMASK(3, 2)
130 #define TMAG5273_MEAS_RANGE_X_Y_MSK GENMASK(1, 1)
131 #define TMAG5273_MEAS_RANGE_Z_MSK GENMASK(0, 0)
199 #define TMAG5273_VER_MSK GENMASK(1, 0)
200 #define TMAG3001_VER_MSK GENMASK(3, 2)
215 #define TMAG5273_DIAG_STATUS_MSK GENMASK(1, 1)
216 #define TMAG5273_RESULT_STATUS_MSK GENMASK(0, 0)
229 #define TMAG5273_INTB_RB_MSK GENMASK(4, 4)
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/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_global_cfg.h23 #define MCHP_GCFG_DEV_ID_REG_MASK GENMASK(31, 0)
25 #define MCHP_GCFG_DID_REV_MASK GENMASK(7, 0)
27 #define MCHP_GCFG_DID_SUB_ID_MASK GENMASK(15, 8)
29 #define MCHP_GCFG_DID_DEV_ID_MASK GENMASK(31, 16)
42 #define MCHP_GCFG_SUB_ID_PKG_MASK GENMASK(3, 0)
51 #define MCHP_GCFG_SUB_ID_FAM_MASK GENMASK(7, 4)
/Zephyr-latest/include/zephyr/drivers/stepper/
Dstepper_trinamic.h34 #define TMC_RAMP_VSTART_MAX GENMASK(17, 0)
36 #define TMC_RAMP_V1_MAX GENMASK(19, 0)
38 #define TMC_RAMP_VMAX_MAX (GENMASK(22, 0) - 512)
40 #define TMC_RAMP_A1_MAX GENMASK(15, 0)
42 #define TMC_RAMP_AMAX_MAX GENMASK(15, 0)
44 #define TMC_RAMP_D1_MAX GENMASK(15, 0)
46 #define TMC_RAMP_DMAX_MAX GENMASK(15, 0)
48 #define TMC_RAMP_VSTOP_MAX GENMASK(17, 0)
50 #define TMC_RAMP_TZEROWAIT_MAX (GENMASK(15, 0) - 512)
52 #define TMC_RAMP_VCOOLTHRS_MAX GENMASK(22, 0)
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/Zephyr-latest/soc/realtek/ec/rts5912/reg/
Dreg_system.h40 #define SYSTEM_I3CCLK_I3C0DIV_Msk GENMASK(1, 0)
42 #define SYSTEM_I3CCLK_I3C1DIV_Msk GENMASK(3, 2)
62 #define SYSTEM_I2CCLK_I2C0CLKDIV_Msk GENMASK(3, 2)
68 #define SYSTEM_I2CCLK_I2C1CLKDIV_Msk GENMASK(7, 6)
74 #define SYSTEM_I2CCLK_I2C2CLKDIV_Msk GENMASK(11, 10)
80 #define SYSTEM_I2CCLK_I2C3CLKDIV_Msk GENMASK(15, 14)
86 #define SYSTEM_I2CCLK_I2C4CLKDIV_Msk GENMASK(19, 18)
92 #define SYSTEM_I2CCLK_I2C5CLKDIV_Msk GENMASK(23, 22)
98 #define SYSTEM_I2CCLK_I2C6CLKDIV_Msk GENMASK(27, 26)
104 #define SYSTEM_I2CCLK_I2C7CLKDIV_Msk GENMASK(31, 30)
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