Searched refs:FIFO (Results 1 – 25 of 81) sorted by relevance
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6 A :dfn:`FIFO` is a kernel object that implements a traditional7 first in, first out (FIFO) queue, allowing threads and ISRs17 Any number of FIFOs can be defined (limited only by available RAM). Each FIFO is20 A FIFO has the following key properties:25 A FIFO must be initialized before it can be used. This sets its queue to empty.27 FIFO data items must be aligned on a word boundary, as the kernel reserves36 FIFO data items are restricted to single active instance across all FIFO37 data queues. Any attempt to re-add a FIFO data item to a queue before41 A data item may be **added** to a FIFO by a thread or an ISR.43 otherwise the item is added to the FIFO's queue.[all …]
8 to a FIFO and serves as the underlying implementation for both :ref:`k_fifo
26 int "Status FIFO and control FIFO heap"31 storing status FIFO and control FIFO words which will be used by the DMA.
32 hex "ESP32 UART TX FIFO Threshold"37 Configure the TX FIFO threshold for ESP32 UART driver.40 hex "ESP32 UART RX FIFO Threshold"45 Configure the RX FIFO threshold for ESP32 UART driver.
30 Port 0 RX Threshold at which the RX FIFO interrupt triggers.37 Port 0 TX Threshold at which the TX FIFO interrupt triggers.53 Port 1 RX Threshold at which the RX FIFO interrupt triggers.60 Port 1 TX Threshold at which the TX FIFO interrupt triggers.
20 bool "RA SCI_B UART FIFO usage enable"24 Enable RA SCI_B FIFO
31 bool "RA SCI UART FIFO usage enable"34 Enable RA SCI FIFO
48 bool "UART 16550 (16-bytes FIFO)"50 This enables support for 16-bytes FIFO if UART controller is 16550.53 bool "UART 16750 (64-bytes FIFO and auto flow control)"55 This enables support for 64-bytes FIFO and automatic hardware59 bool "UART 16950 (128-bytes FIFO and auto flow control)"61 This enables support for 128-bytes FIFO and automatic hardware flow control.
24 int "Number of CAN messages allocated to each RX FIFO"28 Defines the number of CAN messages in each RX FIFO. A separate RX FIFO
15 bool "NXP S32 CANXL uses RX FIFO"18 If this is enabled, NXP S32 CANXL uses RX FIFO.
7 bool "FIFO Partitioning"9 FIFO partition feature32 with the DRAIN bit flag set to allow for the hardware FIFO to be drained
32 bool "FIFO rolls on full"34 Controls the behavior of the FIFO when the FIFO becomes completely35 filled with data. If set, the FIFO address rolls over to zero and the36 FIFO continues to fill with new data. If not set, then the FIFO is41 int "FIFO almost full value"
70 …fifo.put.immediate.kernel - Add data to FIFO (no ctx switch) : …71 …fifo.get.immediate.kernel - Get data from FIFO (no ctx switch) : …72 …fifo.put.alloc.immediate.kernel - Allocate to add data to FIFO (no ctx switch) : …73 …fifo.get.free.immediate.kernel - Free when getting data from FIFO (no ctx switch) : …74 …fifo.get.blocking.k_to_k - Get data from FIFO (w/ ctx switch) : …75 …fifo.put.wake+ctx.k_to_k - Add data to FIFO (w/ ctx switch) : …76 …fifo.get.free.blocking.k_to_k - Free when getting data from FIFO (w/ ctx siwtch) : …77 …fifo.put.alloc.wake+ctx.k_to_k - Allocate to add data to FIFO (w/ ctx switch) : …123 …fifo.put.immediate.kernel - Add data to FIFO (no ctx switch) : …124 …fifo.get.immediate.kernel - Get data from FIFO (no ctx switch) : …[all …]
17 bool "IT8XXX2 I2C FIFO mode"20 This is an option to enable FIFO mode which can reduce25 I2C FIFO mode of it8xxx2 can support I2C APIs including:
55 *data++ = TRNG0->FIFO; in entropy_gecko_trng_read()62 tmp = TRNG0->FIFO; in entropy_gecko_trng_read()
5 on the board using its FIFO with a async and sync transfer to compare
115 The shared memory region is entirely used by a single FIFO.143 This is usual FIFO with a circular buffer:146 * The FIFO is empty if ``rd_idx == wr_idx``.147 * The FIFO has one byte less capacity than the ``data`` buffer length.152 Packets are sent over the FIFO described in the above section.153 One packet can be wrapped around if it occurs at the end of the FIFO buffer.185 #. Write the packet to ``data`` FIFO buffer starting at ``wr_idx``.196 #. Push a single packet to FIFO containing magic data: ``45 6d 31 6c 31 4b 30 72 6e 33 6c 69 34``.
25 int "Size (in bytes) of a FIFO word"29 FIFO word.
19 /* Enable FIFO to avoid losing chars on device wakeup */
15 /* Enable FIFO to avoid losing chars on device wakeup */
30 /* Enable FIFO to avoid losing chars on device wakeup */
22 must be a multiple of TX FIFO block size.39 must be a multiple of RX FIFO block size.83 internal FIFO on to the internal MII/GMII interface, passing through
85 TEST CASE: FIFO #195 TEST CASE: FIFO #2107 TEST CASE: FIFO #3
21 :ref:`FIFO <fifos_v2>` identifying the thread/LED and how many times it has25 FIFO to the device console.
21 | enqueue 1 byte msg in FIFO | NNNNNN|22 | dequeue 1 byte msg in FIFO | NNNNNN|23 | enqueue 4 bytes msg in FIFO | NNNNNN|24 | dequeue 4 bytes msg in FIFO | NNNNNN|
