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Searched refs:DT_CHOSEN (Results 1 – 25 of 216) sorted by relevance

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/Zephyr-latest/soc/snps/qemu_arc/
Dlinker.ld12 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
13 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
14 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
21 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
22 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
23 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
24 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/boards/qemu/arc/
Darc_mpu_regions.c26 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
31 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
32 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
53 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
56 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
57 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
/Zephyr-latest/soc/nxp/s32/s32k3/
Ds32k3xx_startup.S40 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
41 ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
57 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
59 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_itcm))
60 ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_itcm))
70 #if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
72 ldr r1, = DT_REG_ADDR(DT_CHOSEN(zephyr_dtcm))
73 ldr r2, = DT_REG_SIZE(DT_CHOSEN(zephyr_dtcm))
/Zephyr-latest/soc/snps/arc_iot/
Dlinker.ld17 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
23 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
24 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
25 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
26 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/soc/snps/nsim/arc_classic/
Dlinker.ld31 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
32 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
33 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
37 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_flash), reg) && \
38 (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0)
39 #define FLASH_START DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
40 #define FLASH_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/boards/snps/nsim/arc_classic/
Darc_mpu_regions.c58 #if DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0
62 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)),
63 DT_REG_SIZE(DT_CHOSEN(zephyr_sram)),
78 #if DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) > 0
81 DT_REG_ADDR(DT_CHOSEN(zephyr_flash)),
82 DT_REG_SIZE(DT_CHOSEN(zephyr_flash)),
Dhaps_arcv3_init.c11 #define DT_SRAM_NODE_ADDR (DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))
12 #define DT_SRAM_NODE_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) / (1024 * 1024))
/Zephyr-latest/soc/intel/raptor_lake/
Dsoc.h32 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
34 #define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console))
36 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-latest/soc/snps/hsdk/
Dlinker.ld16 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
17 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
18 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
19 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-latest/soc/snps/hsdk4xd/
Dlinker.ld16 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
17 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
18 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-latest/soc/altr/qemu_nios2/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/soc/altr/zephyr_nios2f/
Dlinker.ld14 #define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
15 #define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
17 #define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
18 #define _ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
/Zephyr-latest/soc/gd/gd32/gd32a50x/
Dsoc.c13 register unsigned r0 __asm("r0") = DT_REG_ADDR(DT_CHOSEN(zephyr_sram)); in soc_reset_hook()
15 DT_REG_ADDR(DT_CHOSEN(zephyr_sram)) + DT_REG_SIZE(DT_CHOSEN(zephyr_sram)); in soc_reset_hook()
/Zephyr-latest/soc/st/stm32/common/
Dccm.ld12 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
20 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)))
28 } GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ccm)) AT> ROMABLE_REGION)
/Zephyr-latest/drivers/console/
Dram_console.c22 #elif (CONFIG_RAM_CONSOLE_BUFFER_SIZE > DT_REG_SIZE(DT_CHOSEN(zephyr_ram_console)))
27 __attribute__((__section__(LINKER_DT_NODE_REGION_NAME(DT_CHOSEN(zephyr_ram_console)))))
49 device_map((mm_reg_t *)&ram_console_va, DT_REG_ADDR(DT_CHOSEN(zephyr_ram_console)), in ram_console_init()
/Zephyr-latest/samples/subsys/input/draw_touch_events/src/
Dmain.c16 #if !DT_NODE_EXISTS(DT_CHOSEN(zephyr_touch))
20 #if !DT_NODE_EXISTS(DT_CHOSEN(zephyr_display))
24 #define WIDTH (DT_PROP(DT_CHOSEN(zephyr_display), width))
25 #define HEIGHT (DT_PROP(DT_CHOSEN(zephyr_display), height))
28 #define PIXEL_FORMAT (DT_PROP_OR(DT_CHOSEN(zephyr_display), pixel_format, PIXEL_FORMAT_ARGB_8888))
34 static const struct device *const display_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_display));
35 static const struct device *const touch_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_touch));
/Zephyr-latest/soc/intel/elkhart_lake/
Dsoc.h30 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
34 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-latest/soc/intel/alder_lake/
Dsoc.h34 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
38 #define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console))
/Zephyr-latest/tests/subsys/display/cfb/basic/src/
Dclear.c18 static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_display));
19 static const uint32_t display_width = DT_PROP(DT_CHOSEN(zephyr_display), width);
20 static const uint32_t display_height = DT_PROP(DT_CHOSEN(zephyr_display), height);
Dinvert.c18 static const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_display));
19 static const uint32_t display_width = DT_PROP(DT_CHOSEN(zephyr_display), width);
20 static const uint32_t display_height = DT_PROP(DT_CHOSEN(zephyr_display), height);
/Zephyr-latest/soc/snps/emsdp/
Dlinker.ld17 #if DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_sram), reg) && \
18 (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) > 0)
19 #define SRAM_START DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
20 #define SRAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
/Zephyr-latest/kernel/
Dxip.c34 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)) in z_data_copy()
38 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm)) in z_data_copy()
42 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) in z_data_copy()
/Zephyr-latest/subsys/ipc/rpmsg_service/
Drpmsg_backend.h16 #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm))
17 #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm))
/Zephyr-latest/samples/subsys/ipc/openamp/
Dcommon.h11 #define VDEV_START_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_shm))
12 #define VDEV_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_shm))
/Zephyr-latest/tests/drivers/uart/uart_basic_api/src/
Dtest_uart_config.c29 .baudrate = DT_PROP_OR(DT_CHOSEN(zephyr_console), current_speed, 115200),
38 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_configure()
61 const struct device *const uart_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console)); in test_config_get()

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