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Searched refs:DEV_CFG (Results 1 – 25 of 38) sorted by relevance

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/Zephyr-latest/drivers/gpio/
Dgpio_iproc.c43 #define DEV_CFG(dev) ((const struct gpio_iproc_config *const)(dev)->config) macro
48 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_configure()
65 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_port_get_raw()
75 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_port_set_masked_raw()
87 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_port_set_bits_raw()
98 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_port_clear_bits_raw()
112 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_port_toggle_bits()
126 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_pin_interrupt_configure()
160 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_isr()
195 const struct gpio_iproc_config *const cfg = DEV_CFG(dev); in gpio_iproc_init()
Dgpio_xlnx_ps_bank.c24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config) macro
53 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_pin_configure()
134 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_get()
167 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_set_masked()
196 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_set_bits()
225 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_clear_bits()
254 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_toggle_bits()
294 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_pin_irq_configure()
371 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_get_int_status()
433 const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_bank_init()
Dgpio_xlnx_ps.c23 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_dev_cfg *)(_dev)->config) macro
47 const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_init()
84 const struct gpio_xlnx_ps_dev_cfg *dev_conf = DEV_CFG(dev); in gpio_xlnx_ps_isr()
Dgpio_bcm2711.c42 #define DEV_CFG(dev) ((const struct gpio_bcm2711_config *const)(dev)->config) macro
45 #define RPI_PIN_NUM(dev, n) (DEV_CFG(dev)->offset + n)
129 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_port_get_raw()
144 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_port_set_masked_raw()
168 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_port_set_bits_raw()
182 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_port_clear_bits_raw()
196 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_port_toggle_bits()
291 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_isr()
311 const struct gpio_bcm2711_config *cfg = DEV_CFG(port); in gpio_bcm2711_init()
Dgpio_davinci.c27 #define DEV_CFG(dev) \ macro
154 const struct gpio_davinci_config *config = DEV_CFG(dev); in gpio_davinci_init()
Dgpio_brcmstb.c18 #define DEV_CFG(dev) ((const struct gpio_brcmstb_config *)(dev)->config) macro
/Zephyr-latest/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c45 #define DEV_CFG(_dev) \ macro
79 *cycles = DEV_CFG(dev)->art_clock_freq; in tgpio_intel_cyc_per_sec()
89 if (pin >= DEV_CFG(dev)->max_pins) { in tgpio_intel_pin_disable()
108 if (pin >= DEV_CFG(dev)->max_pins) { in tgpio_intel_periodic_output()
148 if (pin >= DEV_CFG(dev)->max_pins) { in tgpio_intel_config_external_timestamp()
179 if (pin >= DEV_CFG(dev)->max_pins) { in tgpio_intel_read_ts_ec()
202 const struct tgpio_config *cfg = DEV_CFG(dev); in tgpio_init()
/Zephyr-latest/scripts/coccinelle/
Dconst_config_info.cocci68 // asg via macro: struct T * D = DEV_CFG()
78 struct T * D = DEV_CFG(E);
80 // asg via macro to const local: struct T * const D = DEV_CFG()
90 struct T * const D = DEV_CFG(E);
106 // delayed asg via macro: struct T * D; ... ; D = DEV_CFG();
118 D = DEV_CFG(E);
/Zephyr-latest/drivers/clock_control/
Dclock_control_ast10x0.c50 #define DEV_CFG(dev) ((const struct clock_aspeed_config *const)(dev)->config) macro
54 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_on()
75 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_off()
97 const struct device *syscon = DEV_CFG(dev)->syscon; in aspeed_clock_control_get_rate()
/Zephyr-latest/drivers/dma/
Ddma_sedi.c39 #define DEV_CFG(dev) \ macro
249 if ((dev == NULL) || (channel >= DEV_CFG(dev)->chn_num) in dma_sedi_chan_config()
255 const struct dma_sedi_config_info *const info = DEV_CFG(dev); in dma_sedi_chan_config()
274 if ((dev == NULL) || (channel >= DEV_CFG(dev)->chn_num)) { in dma_sedi_reload()
303 if ((dev == NULL) || (channel >= DEV_CFG(dev)->chn_num)) { in dma_sedi_start()
309 const struct dma_sedi_config_info *const info = DEV_CFG(dev); in dma_sedi_start()
345 const struct dma_sedi_config_info *const info = DEV_CFG(dev); in dma_sedi_stop()
363 const struct dma_sedi_config_info *const config = DEV_CFG(dev); in dma_sedi_init()
Ddma_mcux_edma.c116 #define DEV_CFG(dev) \ macro
119 #define DEV_BASE(dev) ((DMA_Type *)DEV_CFG(dev)->base)
128 #define DEV_DMAMUX_BASE(dev, idx) ((DMAMUX_Type *)DEV_CFG(dev)->dmamux_base[idx])
129 #define DEV_DMAMUX_IDX(dev, ch) (ch / DEV_CFG(dev)->channels_per_mux)
132 (ch % DEV_CFG(dev)->channels_per_mux) ^ (DEV_CFG(dev)->dmamux_reg_offset)
177 const struct dma_mcux_edma_config *config = DEV_CFG(dev); in dma_mcux_edma_add_channel_gap()
191 const struct dma_mcux_edma_config *config = DEV_CFG(dev); in dma_mcux_edma_remove_channel_gap()
263 for (i = 0; i < DEV_CFG(dev)->dma_channels; i++) { in dma_mcux_edma_error_irq_handler()
321 if (slot >= DEV_CFG(dev)->dma_requests) { in dma_mcux_edma_configure()
326 if (channel >= DEV_CFG(dev)->dma_channels) { in dma_mcux_edma_configure()
[all …]
/Zephyr-latest/drivers/flash/
Dspi_nor.c63 #define DEV_CFG(_dev_) ((const struct spi_nor_config * const) (_dev_)->config) macro
246 if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && DEV_CFG(dev)->use_4b_addr_opcodes) { in dev_erase_types()
806 if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && DEV_CFG(dev)->use_4b_addr_opcodes) { in spi_nor_read()
898 DEV_CFG(dev)->use_4b_addr_opcodes) { in spi_nor_write()
996 DEV_CFG(dev)->use_4b_addr_opcodes) { in spi_nor_erase()
1040 if (DEV_CFG(dev)->wp_gpios_exist && write_protect == false) { in spi_nor_write_protection_set()
1041 gpio_pin_set_dt(&(DEV_CFG(dev)->wp), 0); in spi_nor_write_protection_set()
1055 if (DEV_CFG(dev)->wp_gpios_exist && write_protect == true) { in spi_nor_write_protection_set()
1056 gpio_pin_set_dt(&(DEV_CFG(dev)->wp), 1); in spi_nor_write_protection_set()
1226 if (IS_ENABLED(ANY_INST_USE_4B_ADDR_OPCODES) && DEV_CFG(dev)->use_4b_addr_opcodes) { in spi_nor_process_bfp()
[all …]
Dflash_cadence_nand.c23 #define DEV_CFG(_dev) ((const struct flash_cadence_nand_config *)(_dev)->config) macro
173 const struct flash_cadence_nand_config *nand_config = DEV_CFG(nand_dev); in flash_cdns_nand_init()
Dflash_cadence_qspi_nor.c36 #define DEV_CFG(dev) ((struct flash_cad_config *)((dev)->config)) macro
/Zephyr-latest/drivers/mbox/
Dmbox_ti_omap.c24 #define DEV_CFG(_dev) ((const struct omap_mailbox_config *)(_dev)->config) macro
64 const struct omap_mailbox_config *cfg = DEV_CFG(dev); in omap_mailbox_isr()
164 const struct omap_mailbox_config *cfg = DEV_CFG(dev); in omap_mailbox_set_enabled()
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns.c19 #define DEV_CFG(_dev) ((const struct sdhc_cdns_config *)(_dev)->config) macro
119 const struct sdhc_cdns_config *sdhc_config = DEV_CFG(dev); in sdhc_cdns_get_host_props()
142 const struct sdhc_cdns_config *sdhc_config = DEV_CFG(dev); in sdhc_cdns_init()
/Zephyr-latest/tests/kernel/device/src/
Dmmio_multireg.c37 #define DEV_CFG(dev) ((struct foo_multireg_config_info *)((dev)->config)) macro
Dmmio.c123 #define DEV_CFG(dev) ((struct foo_mult_config_info *)((dev)->config)) macro
/Zephyr-latest/drivers/counter/
Dcounter_dw_timer.c39 #define DEV_CFG(_dev) ((const struct counter_dw_timer_config *)(_dev)->config) macro
294 const struct counter_dw_timer_config *config = DEV_CFG(timer_dev); in counter_dw_timer_get_freq()
314 const struct counter_dw_timer_config *timer_config = DEV_CFG(timer_dev); in counter_dw_timer_init()
Dcounter_mcux_gpt.c19 #define DEV_CFG(_dev) ((const struct mcux_gpt_config *)(_dev)->config) macro
/Zephyr-latest/drivers/audio/
Dwm8904.c28 #define DEV_CFG(dev) ((const struct wm8904_driver_config *const)dev->config) macro
417 const struct wm8904_driver_config *const dev_cfg = DEV_CFG(dev); in wm8904_configure()
587 const struct wm8904_driver_config *const dev_cfg = DEV_CFG(dev); in wm8904_write_reg()
607 const struct wm8904_driver_config *const dev_cfg = DEV_CFG(dev); in wm8904_read_reg()
/Zephyr-latest/drivers/spi/spi_nxp_lpspi/
Dspi_nxp_lpspi_priv.h28 #define DEV_CFG(_dev) ((const struct spi_mcux_config *)(_dev)->config) macro
/Zephyr-latest/drivers/i2c/
Di2c_omap.c100 #define DEV_CFG(dev) ((const struct i2c_omap_cfg *)(dev)->config) macro
376 const struct i2c_omap_cfg *cfg = DEV_CFG(dev); in i2c_omap_recover_bus()
684 const struct i2c_omap_cfg *cfg = DEV_CFG(dev); in i2c_omap_init()
/Zephyr-latest/include/zephyr/sys/
Ddevice_mmio.h435 #define DEVICE_MMIO_NAMED_ROM_PTR(dev, name) (&(DEV_CFG(dev)->name))
/Zephyr-latest/drivers/timer/
Dti_dmtimer.c28 #define DEV_CFG(_dev) ((const struct ti_dm_timer_config *)(_dev)->config) macro

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