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Searched refs:DEVICE_MMIO_GET (Results 1 – 25 of 37) sorted by relevance

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/Zephyr-latest/drivers/serial/
Duart_xlnx_ps.c233 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in set_baudrate()
291 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_init()
345 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_poll_in()
372 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_poll_out()
604 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_configure()
809 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_config_get()
845 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_fifo_fill()
871 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_fifo_read()
892 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_irq_tx_enable()
906 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_irq_tx_disable()
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Duart_rcar.c115 return sys_read8(DEVICE_MMIO_GET(dev) + offs); in uart_rcar_read_8()
121 sys_write8(value, DEVICE_MMIO_GET(dev) + offs); in uart_rcar_write_8()
127 return sys_read16(DEVICE_MMIO_GET(dev) + offs); in uart_rcar_read_16()
133 sys_write16(value, DEVICE_MMIO_GET(dev) + offs); in uart_rcar_write_16()
Duart_pl011_registers.h42 return (volatile struct pl011_regs *)DEVICE_MMIO_GET(dev); in get_uart()
Duart_hvc_xen.c256 data->intf = (struct xencons_interface *) DEVICE_MMIO_GET(dev); in xen_console_init()
/Zephyr-latest/drivers/sdhc/
Dintel_emmc_host.c60 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in enable_interrupts()
71 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in disable_interrupts()
85 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in clear_interrupts()
93 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_set_voltage()
159 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_set_power()
176 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_disable_clock()
199 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_enable_clock()
218 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in emmc_clock_set()
274 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in set_timing()
359 volatile struct emmc_reg *regs = (struct emmc_reg *)DEVICE_MMIO_GET(dev); in poll_cmd_complete()
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/Zephyr-latest/drivers/syscon/
Dsyscon.c36 *addr = DEVICE_MMIO_GET(dev); in syscon_generic_get_base()
61 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_read_reg()
97 base_address = DEVICE_MMIO_GET(dev); in syscon_generic_write_reg()
/Zephyr-latest/drivers/watchdog/
Dwdt_dw.c58 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in dw_wdt_setup()
78 uintptr_t reg_base = DEVICE_MMIO_GET(dev);
108 uintptr_t reg_base = DEVICE_MMIO_GET(dev);
163 uintptr_t reg_base = DEVICE_MMIO_GET(dev);
216 uintptr_t reg_base = DEVICE_MMIO_GET(dev);
/Zephyr-latest/drivers/clock_control/
Dclock_control_r8a7795_cpg_mssr.c87 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
100 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a7795_cpg_enable_disable_core()
110 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a7795_cpg_enable_disable_core()
162 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a7795_cpg_mssr_start_stop()
Dclock_control_r8a779f0_cpg_mssr.c90 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
95 reg = sys_read32(DEVICE_MMIO_GET(dev) + clk_info->offset); in r8a779f0_cpg_enable_disable_core()
105 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg); in r8a779f0_cpg_enable_disable_core()
156 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a779f0_cpg_mssr_start_stop()
Dclock_control_renesas_cpg_mssr.c107 reg_addr += DEVICE_MMIO_GET(dev); in rcar_cpg_get_divider()
316 uint32_t reg = sys_read32(clk_info->offset + DEVICE_MMIO_GET(dev)); in rcar_cpg_set_rate()
319 rcar_cpg_write(DEVICE_MMIO_GET(dev), clk_info->offset, reg | divider); in rcar_cpg_set_rate()
/Zephyr-latest/drivers/spi/
Dspi_dw.h149 return info->read_func(__sz, (mm_reg_t)DEVICE_MMIO_GET(dev), __off); \
155 info->write_func(__sz, data, (mm_reg_t)DEVICE_MMIO_GET(dev), __off); \
162 info->set_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
169 info->clear_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
176 return info->test_bit_func(__bit, (mm_reg_t)DEVICE_MMIO_GET(dev), __reg_off); \
/Zephyr-latest/drivers/virtualization/
Dvirt_ivshmem.c198 (volatile struct ivshmem_v2_reg *)DEVICE_MMIO_GET(dev); in ivshmem_configure()
299 mbar_regs.phys_addr, DEVICE_MMIO_GET(dev)); in ivshmem_configure()
332 (volatile struct ivshmem_v2_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_get_id()
339 (volatile struct ivshmem_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_get_id()
377 (volatile struct ivshmem_v2_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_int_peer()
384 (volatile struct ivshmem_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_int_peer()
473 (volatile struct ivshmem_v2_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_set_state()
514 (volatile struct ivshmem_v2_reg *) DEVICE_MMIO_GET(dev); in ivshmem_api_enable_interrupts()
/Zephyr-latest/drivers/reset/
Dreset_intel_socfpga.c29 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_status()
44 uintptr_t base_address = DEVICE_MMIO_GET(dev); in reset_intel_soc_update()
/Zephyr-latest/drivers/pinctrl/
Dpinctrl_ti_k3.c28 uintptr_t virt_reg_base = DEVICE_MMIO_GET(dev); in pinctrl_configure_pins()
/Zephyr-latest/drivers/interrupt_controller/
Dintc_intel_vtd.c39 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg32()
46 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg32()
54 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_write_reg64()
61 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_read_reg64()
69 uintptr_t base_address = DEVICE_MMIO_GET(dev); in vtd_send_cmd()
294 data->fault_record_reg = DEVICE_MMIO_GET(dev) + in vtd_fault_event_init()
/Zephyr-latest/drivers/disk/nvme/
Dnvme_controller.c29 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_wait_for_ready()
61 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_disable()
98 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_enable()
142 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_setup_admin_queues()
258 mm_reg_t regs = DEVICE_MMIO_GET(dev); in nvme_controller_gather_info()
Dnvme_cmd.c471 mm_reg_t regs = DEVICE_MMIO_GET(qpair->ctrlr->dev); in nvme_cmd_qpair_process_completion()
640 mm_reg_t regs = DEVICE_MMIO_GET(qpair->ctrlr->dev); in nvme_cmd_qpair_submit_request()
/Zephyr-latest/include/zephyr/sys/
Ddevice_mmio.h315 #define DEVICE_MMIO_GET(dev) (*DEVICE_MMIO_RAM_PTR(dev)) macro
317 #define DEVICE_MMIO_GET(dev) (DEVICE_MMIO_ROM_PTR(dev)->addr) macro
/Zephyr-latest/drivers/mdio/
Dmdio_dwcxgmac.c97 ioaddr = (mem_addr_t)DEVICE_MMIO_GET(dev); in mdio_transfer()
193 ioaddr = (mem_addr_t)DEVICE_MMIO_GET(dev); in mdio_dwcxgmac_initialize()
Dmdio_nxp_enet.c222 data->base = (ENET_Type *)DEVICE_MMIO_GET(config->module_dev); in nxp_enet_mdio_init()
/Zephyr-latest/drivers/hwspinlock/
Dsqn_hwspinlock.c29 return (mem_addr_t)(DEVICE_MMIO_GET(dev) + id * sizeof(uint32_t)); in get_lock_addr()
/Zephyr-latest/tests/kernel/device/src/
Dmmio.c69 regs = DEVICE_MMIO_GET(dev); in ZTEST()
/Zephyr-latest/drivers/i2c/
Di2c_dw.c53 return (uint32_t)DEVICE_MMIO_GET(dev); in get_regs()
1072 base = DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET; in i2c_dw_initialize()
1078 dw->base_addr = (uint32_t)(DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_OFFSET); in i2c_dw_initialize()
1080 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_LOW); in i2c_dw_initialize()
1082 DEVICE_MMIO_GET(dev) + DMA_INTEL_LPSS_REMAP_HI); in i2c_dw_initialize()
Di2c_sedi.c185 ret = sedi_i2c_init(context->sedi_device, config->cb_sedi, DEVICE_MMIO_GET(dev)); in i2c_sedi_init()
/Zephyr-latest/drivers/ptp_clock/
Dptp_clock_nxp_enet.c195 data->base = (ENET_Type *)DEVICE_MMIO_GET(config->module_dev); in ptp_clock_nxp_enet_init()

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