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Searched refs:DEFINE_MM_REG_WRITE (Results 1 – 4 of 4) sorted by relevance

/Zephyr-latest/drivers/spi/
Dspi_dw_regs.h45 DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
47 DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
48 DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
51 DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
56 DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)
58 DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 32)
60 DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 16)
62 DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
Dspi_dw.h151 #define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ macro
295 DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 32)
296 DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 32)
300 DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
301 DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
/Zephyr-latest/drivers/i2c/
Di2c_dw_registers.h167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
186 DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32)
191 DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32)
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Di2c_dw.h144 #define DEFINE_MM_REG_WRITE(__reg, __off, __sz) \ macro