Lines Matching refs:DEFINE_MM_REG_WRITE
167 DEFINE_MM_REG_WRITE(con, DW_IC_REG_CON, 32)
170 DEFINE_MM_REG_WRITE(cmd_data, DW_IC_REG_DATA_CMD, 32)
173 DEFINE_MM_REG_WRITE(ss_scl_hcnt, DW_IC_REG_SS_SCL_HCNT, 32)
174 DEFINE_MM_REG_WRITE(ss_scl_lcnt, DW_IC_REG_SS_SCL_LCNT, 32)
176 DEFINE_MM_REG_WRITE(fs_scl_hcnt, DW_IC_REG_FS_SCL_HCNT, 32)
177 DEFINE_MM_REG_WRITE(fs_scl_lcnt, DW_IC_REG_FS_SCL_LCNT, 32)
179 DEFINE_MM_REG_WRITE(hs_scl_hcnt, DW_IC_REG_HS_SCL_HCNT, 32)
180 DEFINE_MM_REG_WRITE(hs_scl_lcnt, DW_IC_REG_HS_SCL_LCNT, 32)
186 DEFINE_MM_REG_WRITE(intr_mask, DW_IC_REG_INTR_MASK, 32)
191 DEFINE_MM_REG_WRITE(rx_tl, DW_IC_REG_RX_TL, 32)
192 DEFINE_MM_REG_WRITE(tx_tl, DW_IC_REG_TX_TL, 32)
221 DEFINE_MM_REG_WRITE(dma_cr, DW_IC_REG_DMA_CR, 32)
224 DEFINE_MM_REG_WRITE(tdlr, DW_IC_REG_TDLR, 32)
226 DEFINE_MM_REG_WRITE(rdlr, DW_IC_REG_RDLR, 32)
234 DEFINE_MM_REG_WRITE(tar, DW_IC_REG_TAR, 32)
235 DEFINE_MM_REG_WRITE(sar, DW_IC_REG_SAR, 32)