Searched refs:DDR_CTL_REG (Results 1 – 1 of 1) sorted by relevance
| /Zephyr-latest/drivers/memc/ |
| D | sifive_ddr.c | 46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i)) macro
75 DDR_CTL_REG(ddr_ctrl, i) = ddr_ctl_settings[i]; in ddr_writeregmap()
82 return ((DDR_CTL_REG(ddr_ctrl, 0) >> DRAM_CLASS_OFFSET) & 0xF); in ddr_getdramclass()
150 DDR_CTL_REG(ddr_ctrl, 120) |= DISABLE_RD_INTERLEAVE; in ddr_init()
151 DDR_CTL_REG(ddr_ctrl, 21) &= ~OPTIMAL_RMODW_EN; in ddr_init()
152 DDR_CTL_REG(ddr_ctrl, 170) |= WRLVL_EN | DFI_PHY_WRLELV_MODE; in ddr_init()
153 DDR_CTL_REG(ddr_ctrl, 181) |= DFI_PHY_RDLVL_MODE; in ddr_init()
154 DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_EN; in ddr_init()
155 DDR_CTL_REG(ddr_ctrl, 260) |= RDLVL_GATE_EN; in ddr_init()
156 DDR_CTL_REG(ddr_ctrl, 182) |= DFI_PHY_RDLVL_GATE_MODE; in ddr_init()
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